LPC2420FBD208-S NXP Semiconductors, LPC2420FBD208-S Datasheet - Page 43

• Manufacturer Part Number: LPC2420FBD208-S
• Description: MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of LPC2420FBD208-S

• Package: 208LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Ram Size: 82 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 160
• Interface Type: I2C/I2S/SPI/SSP/UART/USB
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 1-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

NXP Semiconductors
LPC2420_60_5
Preliminary data sheet
7.24.4.4 Deep power-down mode
7.24.4.5 Power domains
Deep power-down mode is similar to the Power-down mode, but now the on-chip
regulator that supplies power to the internal logic is also shut off. This produces the lowest
possible power consumption without removing power from the entire chip. Since the Deep
power-down mode shuts down the on-chip logic power supply, there is no register or
memory retention, and resumption of operation involves the same activities as a full chip
reset.
If power is supplied to the LPC2420/2460 during Deep power-down mode, wake-up can
be caused by the RTC Alarm interrupt or by external Reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2420/2460 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the Battery RAM, as long as the external power
to the VBAT pin is maintained.
The LPC2420/2460 provides two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the Battery
RAM.
On the LPC2420/2460, I/O pads are powered by the 3.3 V (V
V
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
V
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
DD(DCDC)(3V3)
DD(3V3)
and V
pins power the on-chip DC-to-DC converter which in turn provides power to
DD(DCDC)(3V3)
Rev. 05 — 24 February 2010
pins together. This approach requires only one 3.3 V power
DD(DCDC)(3V3)
Flashless 16-bit/32-bit microcontroller
). Having the on-chip DC-DC
LPC2420/2460
DD(3V3)
) pins, while the
© NXP B.V. 2010. All rights reserved.
DD(3V3)
43 of 79
) and