LPC2420FBD208-S NXP Semiconductors, LPC2420FBD208-S Datasheet - Page 55

• Manufacturer Part Number: LPC2420FBD208-S
• Description: MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of LPC2420FBD208-S

• Package: 208LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Ram Size: 82 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 160
• Interface Type: I2C/I2S/SPI/SSP/UART/USB
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 1-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

Table 10.
C
Symbol
Common to read and write cycles
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
CSLAV
OELAV
CSLOEL
am
h(D)
CSHOEH
OEHANV
OELOEH
BLSLAV
CSHBLSH
CSLWEL
CSLBLSL
WELDV
CSLDV
WELWEH
BLSLBLSH
WEHANV
L
= 30 pF, T
Parameter
CS LOW to address valid
time
OE LOW to address valid
time
CS LOW to OE LOW time
memory access time
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
BLS LOW to address valid
time
CS HIGH to BLS HIGH time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH
time
WE HIGH to address invalid
time
Dynamic characteristics: Static external memory interface
amb
=
−
40
°
C to 85
[1][2]
[1][6]
°
C, V
[1]
DD(DCDC)(3V3)
Conditions
= V
DD(3V3)
[3][4]
[5]
[3]
[3]
[3]
= 3.0 V to 3.6 V, AHB clock = 1 MHz
Min
−0.29
−0.29
−0.78 + T
(WAITRD − WAITOEN + 1) ×
T
1.29
−0.49
−0.20
−0.59 + (WAITRD −
WAITOEN + 1) × T
−0.39
−0.88
−0.88 + T
WAITWEN)
−0.88
0.68
0
−0.78 + T
(WAITWR − WAITWEN + 1)
−0.88 + T
(WAITWR − WAITWEN + 3)
0 + T
cy(CCLK)
cy(CCLK)
− 8.11
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
× WAITOEN 0 + T
× (1 +
×
×
cy(CCLK)
Typ
0.20
0.20
(WAITRD − WAITOEN + 1) ×
T
4.22
0
0.20
0 + (WAITRD − WAITOEN +
1) × T
0
0.49
0.10 + T
WAITWEN)
0.49
2.54
2.64
0 + T
WAITWEN + 1)
0 + T
WAITWEN + 3)
0.20 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 9.57
× WAITOEN
× (WAITWR −
× (WAITWR −
× (1 +
Max
2.54
2.54
0.49 + T
(WAITRD − WAITOEN + 1) ×
T
5.20
0.20
2.44
0.10 + (WAITRD −
WAITOEN + 1) × T
2.54
0.68
0.20 + T
WAITWEN)
0.98
5.86
4.79
0.10 + T
(WAITWR − WAITWEN + 1)
0.59 + T
(WAITWR − WAITWEN + 3)
2.74 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 12.70
× WAITOEN
× (1 +
×
×
cy(CCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns