P89V51RD2FN NXP Semiconductors, P89V51RD2FN Datasheet - Page 46

• Manufacturer Part Number: P89V51RD2FN
• Description: MCU 8-Bit 89V 80C51 CISC 64KB Flash 5V 40-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P89V51RD2FN

• Package: 40PDIP
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
Fig 21. PCA
6.9 PCA
time base for PCA modules
Module functions:
- 16-bit capture
- 16-bit timer
- 16-bit high speed output
- 8-bit PWM
- watchdog timer (module 4 only)
PCA TIMER/COUNTER
Table 33.
Bit addressable; Reset value: 00H
Table 34.
The PCA includes a special 16-bit Timer that has five 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to operate in one of four
modes: rising and/or falling edge capture, software timer, high-speed output, or PWM.
Each module has a pin associated with it in port 1. Module 0 is connected to P1.3 (CEX0),
module 1 to P1.4 (CEX1), etc. Registers CH and CL contain current value of the free
running up counting 16-bit PCA timer. The PCA timer is a common time base for all five
modules and can be programmed to run at:
frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source
is determined from the CPS1 and CPS0 bits in the CMOD SFR (see
Table
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
16 bits
36).
WDTC - Watchdog control register (address COH) bit allocation
WDTC - Watchdog control register (address COH) bit description
Symbol
-
WDOUT
WDRE
WDTS
WDT
SWDT
7
-
Rev. 05 — 12 November 2009
6
-
Description
Reserved for future use. Should be set to ‘0’ by user programs.
Watchdog output enable. When this bit and WDRE are both set, a
Watchdog reset will drive the reset pin active for 32 clocks.
Watchdog timer reset enable. When set enables a watchdog timer
reset.
Watchdog timer reset flag, when set indicates that a WDT reset
occurred. Reset in software.
Watchdog timer refresh. Set by software to force a WDT reset.
Start watchdog timer, when set starts the WDT. When cleared, stops
the WDT.
5
-
MODULE3
MODULE4
MODULE0
MODULE1
MODULE2
WDOUT
16 bits
4
P89V51RB2/RC2/RD2
1
6
the oscillator frequency,
8-bit microcontrollers with 80C51 core
WDRE
3
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
WDTS
2
002aaa532
Table 35
© NXP B.V. 2009. All rights reserved.
1
WDT
2
1
the oscillator
and
SWDT
46 of 80
0