DS26504L+ Maxim Integrated Products, DS26504L+ Datasheet
DS26504L+
Specifications of DS26504L+
Related parts for DS26504L+
DS26504L+ Summary of contents
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GENERAL DESCRIPTION The DS26504 is a building-integrated timing-supply (BITS) clock-recovery element. It also functions as a basic T1/E1 transceiver. The receiver portion can recover a clock from T1, E1, 64kHz composite clock (64KCC), and 6312kHz synchronization timing interfaces. In ...
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FEATURES .......................................................................................................................7 1.1 G .....................................................................................................................................7 ENERAL 1 ...........................................................................................................................7 INE NTERFACE 1 ITTER TTENUATOR 1 RAMER ORMATTER 1 EST AND IAGNOSTICS 1 ............................................................................................................................8 ONTROL ORT 2. SPECIFICATIONS COMPLIANCE ...................................................................................9 3. ...
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T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40 8 ONTROL EGISTERS 9. E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46 9 ONTROL EGISTERS 9 NFORMATION EGISTERS 10. I/O PIN CONFIGURATION OPTIONS ............................................................................53 11. T1 SYNCHRONIZATION STATUS MESSAGE ...
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I R DENTIFICATION EGISTER 18. FUNCTIONAL TIMING DIAGRAMS .............................................................................111 18 ROCESSOR NTERFACE 18.1.1 Parallel Port Mode.............................................................................................................................. 111 18.1.2 SPI Serial Port Mode.......................................................................................................................... 111 19. OPERATING PARAMETERS .......................................................................................114 20. AC TIMING PARAMETERS AND DIAGRAMS ............................................................116 20 ...
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Figure 3-1. Block Diagram ......................................................................................................................................... 11 Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ......................................................................................... 12 Figure 3-3. Transmit PLL Clock Mux Diagram .......................................................................................................... 12 Figure 3-4. Master Clock PLL Diagram ..................................................................................................................... 13 Figure 13-1. Basic Network Connection .................................................................................................................... 80 ...
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Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 9 Table 2-2. E1-Related Telecommunications Specifications ...................................................................................... 10 Table 5-1. LQFP Pinout ............................................................................................................................................. 22 Table 6-1. Transmit Clock Source ............................................................................................................................. 25 Table 6-2. Internal Termination.................................................................................................................................. 25 Table 6-3. E1 Line Build-Out ..................................................................................................................................... 26 Table ...
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FEATURES 1.1 General 64-pin, 10mm x 10mm LQFP package 3.3V supply with 5V tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG Boundary Scan Driver source code available from the factory 1.2 Line Interface Requires a single master clock ...
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Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats include D4 and ESF Detailed alarm and status reporting with optional interrupt support RCL, RLOS, and RAIS alarms interrupt on change of state ...
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SPECIFICATIONS COMPLIANCE The DS26504 meets all applicable sections of the latest telecommunications specifications including those listed in the following tables. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface ANSI T1.231: Digital Hierarchy–Layer 1 In-Service Performance Monitoring ...
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Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048kbps ITUT G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps ITUT G.772 ITUT G.775 ITUT G.823 ...
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BLOCK DIAGRAMS Figure 3-1. Block Diagram MCLK MASTER CLOCK CLOCK RTIP DATA LIU LIU RRING - DATA RLOS RAIS TNEGO TPOSO TTIP TX LIU TRING THZE TCLKO JTAG PORT JTAG PORT JTAG PORT JTAG PORT JTMS ...
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Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) CLOCK FROM RX + DATA LIU - DATA CLOCK DATA LIU - DATA Figure 3-3. Transmit PLL Clock Mux Diagram TPCR.2 RECOVERED CLOCK TCLK PIN JA CLOCK (HARDWARE MODE ...
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Figure 3-4. Master Clock PLL Diagram 13 of 129 ...
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PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE Transmit PLL Output. This pin can be selected to output the 1544kHz, PLL_OUT O 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL or the internal signal, TX CLOCK. See ...
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Receive Side NAME TYPE Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), 6312 kHz (G.703 Synchronization Interface), or 64kHz (Composite Clock) clock. RCLK O Payload Mode: When payload mode is enabled, this pin outputs a gapped clock based on the ...
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NAME TYPE Receive Alarm Indication Signal T1 Mode: Toggles high when the receive Blue Alarm is detected. RAIS O E1 Mode: Toggles high when the receive AIS is detected. 64KCC Mode: This pin high-impedance state. 6312kHz Mode: ...
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NAME TYPE Data Bus D[6] or Address/Data Bus AD[6]/Transmit Internal Termination Disable A[6]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[6]. AD[6]/ I/O TITD AD[6]: In multiplexed bus operation (BIS[1:0] = 00), it serves ...
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NAME TYPE Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master Out-Slave In A[1]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[1]. AD[1]/ AD[1]: In multiplexed bus operation (BIS[1:0] = 00), it serves ...
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NAME TYPE Address Bus Bit A[4]/Serial Port Clock Phase Select/Line Build-Out Select 2 A4: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[4]. In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and should ...
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NAME TYPE Active-Low Read Input-Data Strobe/Receive Mode Select Bit 2 RD RD(DS)/ I RMODE2 RMODE2: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive side operating mode. Active-Low Chip Select/Remote Loopback Enable CS : This active-low signal must ...
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Line Interface NAME TYPE Master Clock Input. A (50ppm) clock source. This clock is used internally for both clock/data recovery and the jitter attenuator for both T1 and E1 modes. A quartz crystal can be applied across MCLK and ...
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PINOUT Table 5-1. LQFP Pinout PIN TYPE PARALLEL PORT 1 I/O AD2 2 I/O AD3 3 I/O AD4 4 I/O AD5 5 I/O AD6 6 I/O AD7 7, 24, I DVDD 58 8, 22, I DVSS ...
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PIN TYPE PARALLEL PORT 18 O TCLKO 19 O TNEGO 20 O TPOSO 21 I TSER 23 I/O TS_8K_4 25 O RCLK 26 O RS_8K 27 O 400HZ 28 O RSER 29 O RAIS 30 O RLOF_CCE 31 I — ...
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PIN TYPE PARALLEL PORT 59 I BIS1 (DS (R/ I/O AD0 64 I/O AD1 MODE SERIAL HARDWARE PORT BIS1 BIS1 Bus Interface Select Mode 1 Parallel Port Mode: Chip Select ...
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HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to certain functions in the port. Only a subset of the device’s functionality is available in hardware mode. Each register ...
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Line Build-Out Table 6-3. E1 Line Build-Out PIN 13 PIN 12 PIN 75Ω normal 120Ω normal 75Ω with high return loss (Note ...
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Receiver Operating Modes Table 6-5. Receive Path Operating Mode RMODE3 RMODE2 RMODE1 PIN 64 PIN ...
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MCLK Pre-Scaler Table 6-7. MCLK Pre-Scaler for T1 Mode MPS1 MPS0 PIN 16 PIN Table 6-8. MCLK Pre-Scaler for E1 Mode MPS1 ...
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Other Hardware Controller Mode Features Table 6-9. Other Operational Modes PIN RS_8K Mode Select: Selects frame or multiframe pulse at RS_8K pin. RSM 0 = frame mode PIN multiframe mode TS_8K_4 Mode Select ...
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PROCESSOR INTERFACE The DS26504 is controlled via a nonmultiplexed (BIS[1: multiplexed (BIS[1:0] = 00) parallel bus. There is also a serial bus mode option, as well as a hardware mode of operation. The bus interface ...
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CS is removed removed before all 8 bits of the data are read, the remaining data will be lost removed before all 8 bits of data are written to the part, ...
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Register Map Table 7-2. Register Map Sorted By Address ADDRESS TYPE 00 R/W Test Reset Register 01 R/W I/O Configuration Register 1 02 R/W I/O Configuration Register 2 03 R/W T1 Receive Control Register 1 04 R/W T1 Receive ...
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ADDRESS TYPE 42 R/W Transmit Si Align Frame 43 R/W Transmit Si Non-Align Frame 44 R/W Transmit Remote Alarm Bits 45 R/W Transmit Sa4 Bits 46 R/W Transmit Sa5 Bits 47 R/W Transmit Sa6 Bits 48 R/W Transmit Sa7 Bits ...
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Power-Up Sequence The DS26504 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will ...
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Mode Configuration Register Register Name: MCREG Register Description: Mode Configuration Register Register Address: 08h Bit # 7 6 Name TMODE3 TMODE2 Default TMODE3 TMODE2 Mode PIN 62 PIN 48 Bits Receive Mode Configuration ...
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Register Name: TPCR1 Register Description: Transmit PLL Control Register 1 Register Address: 09h Bit # 7 6 Name TPLLOFS1 TPLLOFS0 Default Mode For more information on all the bits in the Transmit PLL control register, ...
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Register Name: TPCR2 Register Description: Transmit PLL Control Register 2 Register Address: 0Ah Bit # 7 6 Name — — Default Bit 0: Transmit Clock Source Select (TPLLOFS2). This bit, along with TPLLOFS0 (TPCR1.7) and TPLLOFS1 (TPCR1.6), is used to ...
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This operation is key in controlling the DS26504 with higher-order languages. Status register bits are divided into two groups: condition bits and event bits. Condition bits are typically ...
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Interrupt Information Registers The Interrupt Information Registers (IIRs) provide an indication of which Status Registers (SR1 to SR4) are generating an interrupt. When an interrupt occurs, the host can read IIR to quickly identify which of the four status ...
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T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26504 is configured via a set of five control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26504 has been ...
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Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — — Default Mode Bit 0: Receive Side D4 Yellow Alarm Select (RD4YM zeros in ...
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Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default RMODEx 0 Mode PINS Bit 0:Transmit Yellow Alarm (TYEL not transmit yellow alarm ...
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Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TFSE Default HBE 1 Mode PIN 55 Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS ...
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Register Name: T1CCR Register Description: T1 Common Control Register Register Address: 07h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper ...
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Table 8-1. T1 Alarm Criterion ALARM Blue Alarm (AIS) (Note 1) D4 Yellow Alarm (RAI) (T1RCR2 Japanese Yellow Alarm (T1RCR2 ESF Yellow Alarm (RAI) Red Alarm (RLOS) (Also known as Loss of Signal) Note 1: The ...
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E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26504 is configured via a set of two control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26504 has been ...
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Table 9-1. E1 Sync/Resync Criterion FRAME OR MULTIFRAME SYNC CRITERION LEVEL FAS FAS present in frame N and and FAS not present in frame CRC4 Two valid MF alignment words found within 8ms CAS ...
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Register Name: E1TCR Register Description: E1 Transmit Control Register Register Address: 1Eh Bit # 7 6 Name TFPT — Default Mode Bit 0: Automatic AIS Generation (AAIS disabled 1 = enabled Bit 1: ...
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E1 Information Registers Register Name: INFO2 Register Description: Information Register 2 Register Address: 12h Bit # 7 6 Name — — Default Mode Bit 0: CAS Resync Criterion Met Event (CASRC). Set when two ...
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Table 9-2. E1 Alarm Criterion ALARM SET CRITERION RLOF An RLOF condition exists on power-up prior to initial synchronization, when a resync criterion has been met, or when a manual resync has been initiated via E1RCR.0 RLOS 255 or 2048 ...
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Register Name: SR2 Register Description: Status Register 2 Register Address: 16h Bit # 7 6 Name RYELC RAISC Default Mode Bit 0: Receive Loss-of-Frame Condition (RLOF). Set when the DS26504 is not synchronized to the ...
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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 17h Bit # 7 6 Name RYELC RAISC Default Mode Bit 0: Receive Loss-of-Frame Condition (RLOF interrupt masked 1 = interrupt enabled–interrupts ...
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I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name G703TE RSMS2 Default Mode Bit 0: Output Data Format (ODF bipolar ...
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Table 10-1. TS_8K_4 Pin Functions TRANSMIT IOCR1.3 IOCR1.2 MODE T1/E1 0 T1/E1 0 T1/E1 0 T1/E1 0 64KCC 0 64KCC 0 64KCC 1 64KCC 1 Table 10-2. RLOF_CCE Pin Functions RECEIVE IOCR1.4 RLOF_CCE PIN FUNCTION MODE T1/E1 0 T1/E1 1 ...
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Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default Mode Bit 0: Receive Payload Clock Output Enable (RPCOE). Setting this bit enables a gapped ...
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T1 SYNCHRONIZATION STATUS MESSAGE The DS26504 has a BOC controller to handle SSM services in T1 mode. Table 11-1. T1 SSM Messages QUALITY LEVEL 1 Stratum 1 Traceable 2 Synchronized Traceablity Unknown 3 Stratum 2 Traceable 4 Stratum 3 ...
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Receive BOC The receive BOC function is enabled by setting BOCC The RFDL register will now operate as the receive BOC message and information register. The lower six bits of the RFDL register (BOC message bits) are ...
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Register Name: BOCC Register Description: BOC Control Register Register Address: 1Fh Bit # 7 6 Name — — Default Mode Bit 0: Send BOC (SBOC). Set = 1 to transmit the BOC code placed in ...
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Register Name: RFDL (RFDL register bit usage when BOCC Register Description: Receive FDL Register Register Address: 50h Bit # 7 6 Name — — Default Mode Bit 0: BOC Bit 0 (RBOC0) Bit ...
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Register Name: SR3 Register Description: Status Register 3 Register Address: 18h Bit # 7 6 Name — LOTC Default Mode Bit 0: Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a ...
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Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 19h Bit # 7 6 Name — LOTC Default Mode Bit 0: Receive BOC Detector Change-of-State Event (RBOC interrupt masked 1 = ...
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Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ah Bit # 7 6 Name — RSA1 Default Mode Bit 0: Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning ...
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Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Bh Bit # 7 6 Name — RSA1 Default Mode Bit 0: Receive Align Frame Event (RAF interrupt masked 1 = interrupt ...
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Register Name: TFDL Register Description: Transmit FDL Register Register Address: 51h Bit # 7 6 Name TFDL7 TFDL6 Default Mode Note: Also used to insert Fs framing pattern in D4 framing mode. The transmit FDL ...
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E1 SYNCHRONIZATION STATUS MESSAGE The DS26504 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to transmit and receive the SSM. The primary method to access the Sa (and Si) bits ...
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Sa Bit Change of State The DS26504 can provide an interrupt whenever one of the multiframe based Sa bit patterns changes. Using the SR5 and IMR5 registers, the user can enable interrupts on a change of state for Sa4, ...
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Register Name: IMR5 Register Description: Interrupt Mask Register 5 Register Address: 22h Bit # 7 6 Name — — Default Mode Bit 0: Sa4 Change of State (Sa4COS interrupt masked 1 = interrupt ...
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Register Name: RsiAF Register Description: Receive Si Bits of the Align Frame Register Address: 58h Bit # 7 6 Name SiF0 SiF2 Default Mode Bit 0: Si Bit of Frame 14(SiF14) Bit 1: Si Bit ...
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Register Name: RRA Register Description: Receive Remote Alarm Register Address: 5Ah Bit # 7 6 Name RRAF1 RRAF3 Default Mode Bit 0: Remote Alarm Bit of Frame 15(RRAF15) Bit 1: Remote Alarm Bit of Frame ...
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Register Name: Rsa5 Register Description: Receive Sa5 Bits Register Address: 5Ch Bit # 7 6 Name Rsa5F1 Rsa5F3 Default Mode Bit 0: Sa5 Bit of Frame 15(Rsa5F15) Bit 1: Sa5 Bit of Frame 13(Rsa5F13) Bit ...
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Register Name: Rsa7 Register Description: Receive Sa7 Bits Register Address: 5Eh Bit # 7 6 Name Rsa7F1 Rsa7F3 Default Mode Bit 0: Sa7 Bit of Frame 15(Rsa7F15) Bit 1: Sa7 Bit of Frame 13(Rsa7F13) Bit ...
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Register Name: TsiAF Register Description: Transmit Si Bits of the Align Frame Register Address: 42h Bit # 7 6 Name TsiF0 TsiF2 Default Mode Bit 0: Si Bit of Frame 14(TsiF14) Bit 1: Si Bit ...
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Register Name: TRA Register Description: Transmit Remote Alarm Register Address: 44h Bit # 7 6 Name TRAF1 TRAF3 Default Mode Bit 0: Remote Alarm Bit of Frame 15(TRAF15) Bit 1: Remote Alarm Bit of Frame ...
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Register Name: Tsa5 Register Description: Transmit Sa5 Bits Register Address: 46h Bit # 7 6 Name Tsa5F1 Tsa5F3 Default Mode Bit 0: Sa5 Bit of Frame 15(Tsa5F15) Bit 1: Sa5 Bit of Frame 13(Tsa5F13) Bit ...
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Register Name: Tsa7 Register Description: Transmit Sa7 Bits Register Address: 48h Bit # 7 6 Name Tsa7F1 Tsa7F3 Default Mode Bit 0: Sa7 Bit of Frame 15(Tsa7F15) Bit 1: Sa7 Bit of Frame 13(Tsa7F13) Bit ...
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Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: 4Ah Bit # 7 6 Name SiAF SiNAF Default Mode Bit 0: Additional Bit 8 Insertion Control Bit (Sa8 not ...
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Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on ...
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Register Name: RNAF Register Description: Receive Non-Align Frame Register Register Address: 57h Bit # 7 6 Name Si 1 Default Mode Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: ...
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Register Name: TNAF Register Description: Transmit Non-Align Frame Register Register Address: 41h Bit # 7 6 Name Si 1 Default 0 1 Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: Additional Bit 6 (Sa6) ...
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LINE INTERFACE UNIT (LIU) The LIU in the DS26504 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which generates waveshapes and drives the network line; and the jitter attenuator. These three sections are controlled ...
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LIU Operation The LIU interfaces the T1, E1, 64KCC, and 6312kHz signals to the various types of network media through coupling transformers. The LIU transmit and receive functions are independent. For example, the receiver can mode ...
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Receive G.703 Section 13 Synchronization Signal The DS26504 can receive a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703. To use the DS26504 in this mode, set the mode configuration bits in the Mode Configuration ...
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The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode, the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the automatic gain mode, ...
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TCLK pin is adjusted to create a smooth jitter-free clock that is used to clock data out of the jitter attenuator FIFO acceptable to provide a gapped/bursty clock at ...
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LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 30h Bit # 7 6 Name L2 L1 Default Mode PIN 13 PIN 12 Bit 0: Transmit Power-Down (TPD) 0 ...
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T1 Mode APPLICATION DSX 133 feet)/0dB CSU DSX-1 (133 to 266 feet DSX-1 (266 to 399 feet DSX-1 (399 to 533 feet) 1 ...
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Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 31h Bit # 7 6 Name JACKS1 LIRST Default Mode Bit 0: Custom Line-Driver Select (CLDS). Setting this bit to a one redefines the ...
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Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 32h Bit # 7 6 Name CMIE CMII Default Mode Bit 0: Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern at TTIP ...
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Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 33h Bit # 7 6 Name MPS1 MPS0 Default MPS1 MPS0 Mode PIN 16 PIN 15 Bits Receive Termination Select (RT0 to RT2) ...
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Bits 6 and 7: MCLK Prescaler (MPS0 and MPS1) (E1 Mode) MCLK MPS1 MPS0 (MHz) 2.048 0 4.096 0 8.192 1 12.8 0 16.384 1 Register Name: INFO1 Register Description: Information Register 1 Register Address: 11h Bit # 7 6 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 14h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper operation. ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 15h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper ...
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Recommended Circuits Figure 13-4. Software-Selected Termination, Metallic Protection F1 TX TIP S3 TX RING F2 RX TIP S4 RX RING Table 13-1. Component List (Software-Selected Termination, Metallic Protection) NAME F1 and F2 1.25A slow blow fuse S1 and S2 ...
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Figure 13-5. Software-Selected Termination, Longitudinal Protection F1 TX TIP RING TIP RING F4 Table 13-2. Component List (Software-Selected Termination, Longitudinal Protection) NAME 1.25A slow blow fuse ...
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Component Specifications Table 13-3. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 ...
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Figure 13-6. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 Figure 13-7. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ...
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Figure 13-8. Jitter Tolerance (T1 Mode) 1K 100 10 1 0.1 1 Figure 13-9. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS26504 DS26502 TOLERANCE Tolerance TR 62411 (Dec. 90) ITU-T G.823 10 100 1K FREQUENCY (Hz) ...
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Figure 13-10. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 13-11. Jitter Attenuation (E1 Mode) 0dB -20dB -40dB -60dB 1 DS26502 DS26504 T1 MODE T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area Prohibited Area DS26502 DS26504 ...
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LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Address: 20h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 ...
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SYNCHRONIZATION INTERFACE The 64kHz synchronization interface conforms to Appendix II of G.703. It consists of a composite clock, where a 64kHz clock signal is generated or decoded, along with embedded frequencies of 8kHz and 400Hz. Those signals consist ...
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Transmit 64kHz Synchronization Interface Operation In the transmit path, the framer generateS the appropriate AMI waveform with the correct bipolar violations as described by G.703 and GR.378 8kHz signal is present on the TS_8K_4 pin, the bipolar ...
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SYNCHRONIZATION INTERFACE The DS26504 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix II.2 of G.703, with the exception that the DS26504 transmits a square wave as opposed to the sine wave that is defined ...
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JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26504 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26504 contains the following as required by IEEE ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 17-2. Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. ...
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Select-IR-Scan All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. ...
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Figure 17-2. TAP Controller State Diagram Test Logic 1 Reset 0 Run Test/ 0 Idle 1 1 Select DR-Scan Capture DR 0 Shift Exit DR 0 Pause Exit2 ...
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Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and ...
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IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the capture-DR ...
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Table 17-4. Boundary Scan Control Bits CELL # NAME 0 AD1 1 AD1_7_CTRL 2 AD0 3 AD0_CTRL 4 WR_RW 5 RD_DS BIS1 8 BIS0 9 BTS 10 THZE 11 TMODE1 12 TMODE2 13 PLL_CLK 14 INT 15 ...
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CELL # NAME 29 TNEGO observe_only 30 TCLKO observe_only 31 TCLK observe_only 32 ALE_A7 observe_only 33 A6 observe_only 34 A5 observe_only 35 A4 observe_only 36 A3 observe_only 37 A2 observe_only 38 A1 observe_only 39 A0 observe_only 40 AD7 41 AD6 ...
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FUNCTIONAL TIMING DIAGRAMS 18.1 Processor Interface 18.1.1 Parallel Port Mode See the AC Timing section. 18.1.2 SPI Serial Port Mode Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 SCK CS MOSI 1 0 ...
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Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 SCK CS MOSI MSB MISO Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 SCK CS ...
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Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 SCK CS MOSI MSB MISO Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 SCK CS ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS26504L…………………………………………………………0°C to +70°C Operating Temperature Range for DS26504LN……………………………………………-40°C to +85°C (Note 1) Storage Temperature Range………………………………………………………………………...-55°C to +125°C Soldering Temperature………………………………………………….….See IPC/JEDEC ...
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Table 19-5. DC Characteristics = 3.3V ±5 0°C to +70°C for DS26504L DS26504LN.) PARAMETER SYMBOL Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) Note 6: 0.0V < V < V ...
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AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals and 20pF for all others. 20.1 Multiplexed Bus Table 20-1. AC Characteristics, Multiplexed Parallel Port = 3.3V ±5 0°C to +70°C for DS26504L; ...
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Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) ALE t ASD AD0-AD7 Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00) ALE t ASD RD t ASD WR ...
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Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1: ASD AD0-AD7 (read) CS AD0-AD7 (write) A8 & ASH t ASED t RWS t t DDR ASL t AHL ...
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Nonmultiplexed Bus Table 20-2. AC Characteristics, Nonmultiplexed Parallel Port = 3.3V ±5 0°C to +70°C for DS26504L DS26504LN.) (Note 1) (Figure PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup ...
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Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1: 0ns min RD Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1: ...
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Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1: 0ns min. DS Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1: ...
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Serial Bus Table 20-3. AC Characteristics, Serial Bus = 3.3V ±5 0°C to +70°C for DS26504L DS26504LN.) (Note 1) (Figure 20-8 DIAGRAM CHARACTERISTIC (Note 3) NUMBER Operating Frequency (Note 2) Slave 1 Cycle ...
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Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1: INPUT CLK INPUT CPOL = 0 2 CLK INPUT CPOL = 1 8 MISO INPUT 6 MOSI OUTPUT NOTE: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST ...
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Receive Side AC Characteristics Table 20-4. Receive Side AC Characteristics = 3.3V ±5 0°C to +70°C for DS26504L DS26504LN.) (Note 1) (Figure PARAMETER RCLK Period RCLK Pulse Width RCLK Pulse Width RCLK to ...
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Figure 20-10. Receive Timing—T1, E1, 64KCC Mode RCLK t D1 RSER RS_8K 1 RS_8K 2 400HZ 3 NOTES: 1) RS_8K OUTPUT MODE. 2) RS_8K OUTPUT IN 64KCC MODE. 3) 400Hz OUTPUT ACTIVE ONLY IN 64KCC MODE, ...
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Transmit Side AC Characteristics Table 20-5. Transmit Side AC Characteristics = 3.3V ±5 -40°C to +85°C.) (Note PARAMETER TCLK Period TCLK Pulse Width TCLK Rise and Fall Times TX CLOCK Setup to ...
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Figure 20-11. Transmit Timing—T1, E1, 64KCC Mode t R TCLK RCLK, JA CLOCK 4 PLL_OUT TX CLOCK 3 TSER TS_8K_4 1 TS_8K_4 2 (REFER TO THE TRANSMIT PLL BLOCK DIAGRAM, 3-3.) NOTE 1: TS_8K_4 IN OUTPUT MODE. NOTE 2: TS_8K_4 ...
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REVISION HISTORY REVISION DATE 070105 New product release. 081105 Corrected the polarity of the TAIS pin when operating in Hardware mode. Changed Section 13.4 to read “2.048 x 2 101805 “2.048 x N (where 4).” ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor. DS26504 T1/E1/J1/64KCC BITS Element 129 of 129 © ...