A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet
A3P125-QNG132
Specifications of A3P125-QNG132
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A3P125-QNG132 Summary of contents
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... Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 350 MHz) SRAMs • Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available) A3P060 A3P125 60 k 125 k 1,536 3,072 18 36 ...
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... Each used differential I/O pair reduces the number of available single-ended I/Os by two. 3. FG256 and FG484 are footprint-compatible packages. Automotive ProASIC3 Device Status Automotive ProASIC3 Devices A3P060 A3P125 A3P250 A3P1000 I I A3P125 A3P250 I/O Type – 157 – ...
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... Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number Automotive ProASIC3 Devices A3P060 = 60,000 System Gates A3P125 = 125,000 System Gates A3P250 = 250,000 System Gates A3P1000 = 1,000,000 System Gates Note: Minimum order quantities apply. Contact your local Actel sales office for details. ...
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... T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100 Grade 2 = 105°C T and 115° Grade 1 = 125°C T and 135° Specifications for Commercial and Industrial grade devices can be found in the Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx A3P125 – – – – A3P250 A3P1000 – ...
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Table of Contents Automotive ProASIC3 Device Family Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Automotive ProASIC3 Device Family Overview General Description Automotive ProASIC3 nonvolatile flash technology gives automotive system designers the advantage of a secure, low-power, single-chip solution that is live at power-up (LAPU). Automotive ProASIC3 is reprogrammable and offers time-to-market benefits ...
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Automotive ProASIC3 Device Family Overview valuable IP is protected and secure. An Automotive ProASIC3 device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration ...
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... In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of Automotive ProASIC3 devices via an IEEE 1532 JTAG interface. ISP AES Decryption Figure 1-1 • Automotive ProASIC3 Device Architecture Overview with Two I/O Banks (A3P060 and A3P125) Automotive ProASIC3 Flash Family FPGAs 1-4): Bank 0 ...
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Automotive ProASIC3 Device Family Overview ISP AES User Nonvolatile Decryption FlashROM Figure 1-2 • Automotive ProASIC3 Device Architecture Overview with Four I/O Banks (A3P600 and A3P1000) VersaTiles The Automotive ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ...
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User Nonvolatile FlashROM Actel Automotive ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Unique protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory ...
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Automotive ProASIC3 Device Family Overview • Clock frequency synthesis (for PLL only) Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). • Output duty ...
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Automotive ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximums are stress ratings only; functional operation of the ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Junction temperature J VCC 1 core supply voltage VJTAG JTAG DC voltage VPUMP Programming voltage VCCPLL Analog power supply (PLL) VCCI and 1.5 V ...
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Table 2-3 • Overshoot and Undershoot Limits (as measured on quiet I/Os) VCCI and Average VCCI–GND Overshoot or Undershoot VMV Duration as a Percentage of Clock Cycle 2 less 3 V 3.3 V 3.6 V Notes: 1. The ...
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Automotive ProASIC3 DC and Switching Characteristics VCC = VCCI + VT where VT can be from 0. 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF VCC = 1.425 V Activation ...
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Package Thermal Characteristics The device junction-to-case thermal resistivity is θ θ . The thermal characteristics for θ ja temperature is 110° allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (°C) ...
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... V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes the static power (where applicable) measured on VMV. DC2 the total dynamic power measured on V AC9 A3P060 A3P125 Table 2-7 and Table 2-10 on page 2-8. Static Power VMV (V) P (mW) DC2 3.3 – ...
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Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-10 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 ...
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... P is the total static power consumption. STAT P is the total dynamic power consumption. DYN Definition A3P1000 A3P250 A3P125 A3P060 ® Integrated Design Environment (IDE). 2-12. The calculation should be repeated for each clock domain defined in the TOTAL Automotive ProASIC3 Flash Family FPGAs Device Specific Dynamic Power (µ ...
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Automotive ProASIC3 DC and Switching Characteristics Total Static Power Consumption— STAT DC1 N is the number of I/O input buffers used in the design. INPUTS N is the number of I/O output buffers used in ...
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I/O Output Buffer Contribution— OUTPUTS OUTPUTS N is the number of I/O output buffers used in the design. OUTPUTS α is the I/O buffer toggle rate—guidelines are provided in 2 β is the I/O buffer enable ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation Component β 1 β 2 β 3 User I/O Characteristics Timing Model I/O Module (registered 1. LVPECL D Q (applicable ...
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PY PAD t = MAX MAX(t DIN V trip PAD 50% Y GND t PY (R) DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example) Automotive ProASIC3 Flash Family FPGAs t DIN D ...
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Automotive ProASIC3 DC and Switching Characteristics D CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example DOUT Q DOUT t = MAX MAX(t DOUT ...
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EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip VOL D 50 EOUT (R) VCC 50% EOUT t ZLS PAD Vtrip VOL Figure ...
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Automotive ProASIC3 DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and ...
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Table 2-16 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard I/O Banks Drive Slew Min. I/O Standard Strength Rate V 3.3 V LVTTL / 8 mA ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-19 • I/O AC Parameter Definitions Parameter t Data-to-Pad delay through the Output Buffer DP t Pad-to-Data delay through the Input Buffer PY t Data–to–Output Buffer delay through the I/O interface DOUT t ...
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Table 2-21 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Automotive-Case Conditions: T Worst Case VCCI = 3.0 V Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 35 pF 3.3 V LVCMOS ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-22 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Automotive-Case Conditions: T Worst Case VCCI = 3.0 V Advanced I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High ...
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Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Automotive-Case Conditions: T Worst Case VCCI = 3.0 V Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 35 pF 3.3 V LVCMOS ...
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Automotive ProASIC3 DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-24 • Input Capacitance Symbol C Input capacitance IN C Input capacitance on the clock pin INCLK Table 2-25 • I/O Output Buffer Maximum Resistances Applicable to Advanced I/O ...
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Table 2-26 • I/O Output Buffer Maximum Resistances Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X Notes: 1. These maximum values are ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-28 • I/O Short Currents I Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X ...
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Table 2-29 • I/O Short Currents I OSH Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI 100°C J The length ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-31 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS LVDS/B-LVDS/M- LVDS/LVPECL * The maximum input rise/fall time is related to the noise induced into the input buffer ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-32 • Minimum and Maximum DC ...
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Automotive ProASIC3 DC and Switching Characteristics Test Point Datapath Figure 2-7 • AC Loading Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low ( Measuring point = V See Table 2-18 on page 2-17 trip. ...
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Timing Characteristics Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 8.56 -1 0.55 7. ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t DOUT 4 mA STD 0.64 8.06 -1 0.55 ...
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Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.63 8.28 -1 0.53 7. STD 0.63 ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t DOUT 4 mA STD 0.63 7.79 -1 0.55 ...
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V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-43 • Minimum and Maximum ...
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Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-46 • 2.5 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 9.69 -1 0.55 8.24 ...
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Table 2-48 • 2.5 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 9.26 -1 0.55 7. STD 0.64 5.43 -1 0.55 ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-50 • 2.5 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 2 mA STD 0.63 9.37 -1 0.53 7. STD ...
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Table 2-52 • 2.5 V LVCMOS High Slew Automotive-Case Conditions 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT STD ...
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Automotive ProASIC3 DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output ...
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Timing Characteristics Table 2-57 • 1.8 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 13.26 -1 0.55 11. STD 0.64 7.73 -1 ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-58 • 1.8 V LVCMOS Low Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 17.36 -1 0.55 14. ...
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Table 2-60 • 1.8 V LVCMOS Low Slew Automotive-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 17.36 -1 0.55 14. STD 0.64 11.71 -1 0.55 ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-62 • 1.8 V LVCMOS Low Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.63 16.80 -1 0.53 14. ...
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Table 2-64 • 1.8 V LVCMOS Low Slew Automotive-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT STD 0.63 16.80 -1 0.53 14. STD 0.63 11.33 -1 0.53 ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-66 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL Drive Min. Max. Strength –0.3 0.30 * VCCI 0.7 ...
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Timing Characteristics Table 2-68 • 1.5 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 9.35 -1 0.55 7. STD 0.64 5.94 -1 ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-70 • 1.5 V LVCMOS High Slew Automotive-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT STD 0.64 8.76 -1 0.55 7.45 4 ...
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Table 2-73 • 1.5 V LVCMOS Low Slew Automotive-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT STD 0.63 13.83 -1 0.53 11. STD 0.63 10.83 -1 0.53 9.21 ...
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Automotive ProASIC3 DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-76 • Minimum and Maximum DC Input and ...
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Table 2-80 • 3.3 V PCI/PCI-X Automotive-Case Conditions: T Applicable to Advanced I/O Banks Speed Grade t t DOUT DP Std. 0.628 2.50 0.05 –1 0.53 2.12 0.04 Note: For specific junction temperature and voltage supply levels, refer to Table ...
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Automotive ProASIC3 DC and Switching Characteristics FPGA OUTBUF_LVDS P N Figure 2-12 • LVDS Circuit Diagram and Board-Level Implementation Table 2-82 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI Supply Voltage VOL Output Low Voltage VOH ...
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B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive ...
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Automotive ProASIC3 DC and Switching Characteristics FPGA P OUTBUF_LVPECL N Figure 2-14 • LVPECL Circuit Diagram and Board-Level Implementation Table 2-86 • Minimum and Maximum DC Input and Output Levels DC Parameter Description V Supply Voltage CCI V Output Low ...
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I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset PRE Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-15 • ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-90 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the ...
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-16 • Timing Model of ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-91 • Parameter Definitions and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the ...
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Input Register 50% 50% CLK t ISUD 1 50% Data Enable 50% t IHE t ISUE Preset Clear Out_1 Figure 2-17 • Input Register Timing Diagram Timing Characteristics Table 2-92 • Input Data Register Propagation Delays Automotive-Case Conditions: T Parameter ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-93 • Input Data Register Propagation Delays Automotive-Case Conditions: T Parameter t Clock-to-Q of the Input Data Register ICLKQ t Data Setup Time for the Input Data Register ISUD t Data Hold Time ...
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Output Register 50% 50% CLK 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-18 • Output Register Timing Diagram Timing Characteristics Table 2-94 • Output Data Register Propagation Delays Automotive-Case Conditions: T Parameter t Clock-to-Q ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-95 • Output Data Register Propagation Delays Automotive-Case Conditions: T Parameter t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time ...
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Output Enable Register 50% 50% CLK t OESUD 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-19 • Output Enable Register Timing Diagram Timing Characteristics Table 2-96 • Output Enable Register Propagation Delays Automotive-Case ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-97 • Output Enable Register Propagation Delays Automotive-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register OESUD t Data Hold Time ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-20 • Input DDR Timing Model Table 2-98 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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Automotive ProASIC3 DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-21 • Input DDR Timing Diagram Timing Characteristics Table 2-99 • Input DDR Propagation Delays Automotive-Case Conditions 135°C, ...
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Table 2-100 • Input DDR Propagation Delays Automotive-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR DDRICLKQ2 t Data Setup for Input DDR DDRISUD t Data Hold for Input DDR DDRIHD t ...
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Automotive ProASIC3 DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-22 • Output DDR Timing Model Table 2-101 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q ...
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CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-23 • Output DDR Timing Diagram Timing Characteristics Table 2-102 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-103 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for Output DDR DDROCLKQ t Data_F Data Setup for Output DDR DDROSUD1 t Data_R Data Setup for Output DDR ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the and ProASIC3/E Macro ...
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Automotive ProASIC3 DC and Switching Characteristics OUT GND VCC OUT Figure 2-25 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic t = MAX PD(RR) where ...
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Timing Characteristics Table 2-104 • Combinatorial Cell Propagation Delays Automotive-Case Conditions: T Combinatorial Cell INV AND2 · B NAND2 Y = !(A · B) OR2 NOR2 Y = !(A ...
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Automotive ProASIC3 DC and Switching Characteristics VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-27 • Timing Model and Waveforms Timing Characteristics Table 2-106 • Register Delays Automotive-Case Conditions: T Parameter t Clock-to-Q of the ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-107 • Register Delays Automotive-Case Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time for the Core Register HD ...
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Global Resource Characteristics A3P250 Clock Tree Topology Clock delays are device-specific. global tree presented in Figure 2-28 is used to drive all D-flip-flops in the device. CCC Figure 2-28 • Example of Global Tree Use in an A3P250 Device for ...
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Automotive ProASIC3 DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and ...
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... Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-111 • A3P125 Global Resource Commercial-Case Conditions: T Parameter ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-112 • A3P250 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock ...
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Table 2-114 • A3P1000 Global Resource Automotive-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH t Minimum Pulse Width Low ...
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Automotive ProASIC3 DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-116 • Automotive ProASIC3 CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks ...
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Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-29 • Peak-to-Peak Jitter Definition Automotive ProASIC3 Flash Family FPGAs T T period_max period_min = T – T peak-to-peak period_max period_min ...
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Automotive ProASIC3 DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM4K9 ADDRA11 DOUTA8 DOUTA7 ADDRA10 ADDRA0 DOUTA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 DOUTB8 ADDRB10 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 ...
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Timing Waveforms t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-31 • RAM Read for Pass-Through Output t CKH CLK ADD 0 t ...
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Automotive ProASIC3 DC and Switching Characteristics t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-33 • RAM Write, Output Retained (WMODE = 0) CLK ...
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CLK1 ADD1 DI1 CCKH CLK2 WEN_B1 WEN_B2 A ADD2 DI2 D DO2 D (pass-through) DO2 D (pipelined) Figure 2-35 • Write Access after Write to Same Address ...
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Automotive ProASIC3 DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-36 • Read Access after Write to Same Address ...
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CLK1 ADD1 A 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A D DI2 WEN_B2 Figure 2-37 • Write Access after Read to Same Address t CKH CLK ...
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Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-117 • RAM4K9 Automotive-Case Conditions: T Parameter Description t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t ...
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Table 2-118 • RAM512X18 Automotive-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t Input data (DI) Setup Time DS t Input data ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-119 • RAM4K9 Automotive-Case Conditions: T Parameter Description t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup ...
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Table 2-120 • RAM512X18 Automotive-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t Input data (DI) Setup Time DS t Input data ...
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Automotive ProASIC3 DC and Switching Characteristics FIFO Figure 2-39 • FIFO Model 2- 92 FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-40 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Assertion Automotive ...
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Automotive ProASIC3 DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-42 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY ...
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Timing Characteristics Table 2-121 • FIFO Worst-Case Automotive Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS ...
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Automotive ProASIC3 DC and Switching Characteristics Table 2-122 • FIFO Worst-Case Automotive Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data ...
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Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-45 • Timing Diagram Timing Characteristics Table 2-123 • Embedded FlashROM Access Time Automotive-Case Conditions: T Parameter t Address Setup Time SU t Address Hold Time HOLD ...
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Automotive ProASIC3 DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" ...
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Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Automotive ProASIC3 Flash Family FPGAs ...
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Package Pin Assignments 100-Pin VQFP Pin Number A3P060 Function 1 GND 2 GAA2/IO51RSB1 3 IO52RSB1 4 GAB2/IO53RSB1 5 IO95RSB1 6 GAC2/IO94RSB1 7 IO93RSB1 8 IO92RSB1 9 GND 10 GFB1/IO87RSB1 11 GFB0/IO86RSB1 12 VCOMPLF 13 GFA0/IO85RSB1 14 VCCPLF 15 GFA1/IO84RSB1 16 ...
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VQFP Pin Number A3P250 Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO112PSB3 9 GND 10 GFB1/IO109PDB3 11 GFB0/IO109NDB3 12 VCOMPLF 13 GFA0/IO108NPB3 14 VCCPLF 15 GFA1/IO108PPB3 16 GFA2/IO107PSB3 17 VCC ...
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Package Pin Assignments 132-Pin QFN D4 A36 B33 C30 C21 B23 A25 D3 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package ...
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... IO95RSB1 B17 GND B18 IO87RSB1 B19 IO81RSB1 B20 GND B21 GNDQ B22 TMS B23 TDO B24 GDC0/IO62RSB0 132-Pin QFN Pin Number A3P125 Function B25 GND B26 NC B27 GCB2/IO58RSB0 B28 GND B29 GCB0/IO54RSB0 B30 GCC1/IO51RSB0 B31 GND B32 GBB2/IO43RSB0 B33 VMV0 B34 ...
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... Package Pin Assignments 132-Pin QFN Pin Number A3P125 Function C17 IO83RSB1 C18 VCCIB1 C19 TCK C20 VMV1 C21 VPUMP C22 VJTAG C23 VCCIB0 C24 NC C25 NC C26 GCA1/IO55RSB0 C27 GCC0/IO52RSB0 C28 VCCIB0 C29 IO42RSB0 C30 GNDQ C31 GBA1/IO40RSB0 C32 GBB0/IO37RSB0 C33 VCC ...
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QFN Pin Number A3P250 Function A1 GAB2/IO117UPB3 A2 IO117VPB3 A3 VCCIB3 A4 GFC1/IO110PDB3 A5 GFB0/IO109NPB3 A6 VCCPLF A7 GFA1/IO108PPB3 A8 GFC2/IO105PPB3 A9 IO103NDB3 A10 VCC A11 GEA1/IO98PPB3 A12 GEA0/IO98NPB3 A13 GEC2/IO95RSB2 A14 IO91RSB2 A15 VCC A16 IO90RSB2 A17 IO87RSB2 ...
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Package Pin Assignments 132-Pin QFN Pin Number A3P250 Function C17 IO74RSB2 C18 VCCIB2 C19 TCK C20 VMV2 C21 VPUMP C22 VJTAG C23 VCCIB1 C24 IO53NSB1 C25 IO51NPB1 C26 GCA1/IO50PPB1 C27 GCC0/IO48NDB1 C28 VCCIB1 C29 IO42NDB1 C30 GNDQ C31 GBA1/IO40RSB0 C32 ...
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FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Automotive ProASIC3 Flash Family FPGAs A1 Ball Pad Corner ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P060 Function A1 GNDQ A2 VMV0 A3 GAB0/IO04RSB0 A4 GAB1/IO05RSB0 A5 IO08RSB0 A6 GND A7 IO11RSB0 A8 VCC A9 IO16RSB0 A10 GBA0/IO23RSB0 A11 GBA1/IO24RSB0 A12 GNDQ B1 GAB2/IO53RSB1 B2 GND B3 GAA0/IO02RSB0 B4 ...
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FBGA Pin Number A3P060 Function K1 GEB0/IO74RSB1 K2 GEA1/IO73RSB1 K3 GEA0/IO72RSB1 K4 GEA2/IO71RSB1 K5 IO65RSB1 K6 IO64RSB1 K7 GND K8 IO57RSB1 K9 GDC2/IO56RSB1 K10 GND K11 GDA0/IO50RSB0 K12 GDB0/IO48RSB0 L1 GND L2 VMV1 L3 GEB2/IO70RSB1 L4 IO67RSB1 L5 VCCIB1 ...
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... IO46RSB0 F1 GFB0/IO123RSB1 F2 VCOMPLF F3 GFB1/IO124RSB1 F4 IO127RSB1 F5 GND F6 GND F7 GND F8 GCC0/IO52RSB0 F9 GCB0/IO54RSB0 F10 GND F11 GCA1/IO55RSB0 F12 GCA2/IO57RSB0 R e visio n 1 144-Pin FBGA Pin Number A3P125 Function G1 GFA1/IO121RSB1 G2 GND G3 VCCPLF G4 GFA0/IO122RSB1 G5 GND G6 GND G7 GND G8 GDC1/IO61RSB0 G9 IO48RSB0 G10 GCC2/IO59RSB0 G11 IO47RSB0 G12 GCB2/IO58RSB0 H1 VCC H2 ...
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... FBGA Pin Number A3P125 Function K1 GEB0/IO109RSB1 K2 GEA1/IO108RSB1 K3 GEA0/IO107RSB1 K4 GEA2/IO106RSB1 K5 IO100RSB1 K6 IO98RSB1 K7 GND K8 IO73RSB1 K9 GDC2/IO72RSB1 K10 GND K11 GDA0/IO66RSB0 K12 GDB0/IO64RSB0 L1 GND L2 VMV1 L3 GEB2/IO105RSB1 L4 IO102RSB1 L5 VCCIB1 L6 IO95RSB1 L7 IO85RSB1 L8 IO74RSB1 L9 TMS L10 VJTAG L11 VMV1 L12 TRST M1 GNDQ M2 GEC2/IO104RSB1 M3 IO103RSB1 M4 IO101RSB1 M5 IO97RSB1 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P250 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO29RSB0 A8 VCC A9 IO33RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO117UDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...
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FBGA Pin Number A3P250 Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 GEB2/IO96RSB2 L4 IO91RSB2 L5 VCCIB2 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P1000 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 A8 VCC A9 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...
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FBGA Pin Number A3P1000 Function K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 GEB2/IO186RSB2 L4 IO172RSB2 L5 VCCIB2 ...
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Package Pin Assignments 256-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...
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FBGA Pin Number A3P250 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO07RSB0 A6 IO10RSB0 A7 IO11RSB0 A8 IO15RSB0 A9 IO20RSB0 A10 IO25RSB0 A11 IO29RSB0 A12 IO33RSB0 A13 GBB1/IO38RSB0 A14 GBA0/IO39RSB0 A15 GBA1/IO40RSB0 A16 GND B1 GAB2/IO117UDB3 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P250 Function G13 GCC1/IO48PPB1 G14 IO47NPB1 G15 IO54PDB1 G16 IO54NDB1 H1 GFB0/IO109NPB3 H2 GFA0/IO108NDB3 H3 GFB1/IO109PPB3 H4 V COMPLF H5 GFC0/IO110NPB3 GND H8 GND H9 GND H10 GND H11 ...
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FBGA Pin Number A3P250 Function P9 IO76RSB2 P10 IO71RSB2 P11 IO66RSB2 P12 NC P13 TCK P14 V PUMP P15 TRST P16 GDA0/IO60VDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 R8 IO80RSB2 R9 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P1000 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO22RSB0 A7 IO28RSB0 A8 IO35RSB0 A9 IO45RSB0 A10 IO50RSB0 A11 IO55RSB0 A12 IO61RSB0 A13 GBB1/IO75RSB0 A14 GBA0/IO76RSB0 A15 GBA1/IO77RSB0 A16 ...
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FBGA Pin Number A3P1000 Function G13 GCC1/IO91PPB1 G14 IO90NPB1 G15 IO88PDB1 G16 IO88NDB1 H1 GFB0/IO208NPB3 H2 GFA0/IO207NDB3 H3 GFB1/IO208PPB3 H4 V COMPLF H5 GFC0/IO209NPB3 GND H8 GND H9 GND H10 GND H11 V CC H12 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P1000 Function P9 IO137RSB2 P10 IO134RSB2 P11 IO128RSB2 P12 VMV1 P13 TCK P14 V PUMP P15 TRST P16 GDA0/IO113NDB1 R1 GEA1/IO188PDB3 R2 GEA0/IO188NDB3 R3 IO184RSB2 R4 GEC2/IO185RSB2 R5 IO168RSB2 R6 IO163RSB2 R7 IO157RSB2 ...
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FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...
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Package Pin Assignments 484-Pin FBGA* Pin Number A3P1000 Function A1 GND A2 GND CCI A4 IO07RSB0 A5 IO09RSB0 A6 IO13RSB0 A7 IO18RSB0 A8 IO20RSB0 A9 IO26RSB0 A10 IO32RSB0 A11 IO40RSB0 A12 IO41RSB0 A13 IO53RSB0 A14 IO59RSB0 A15 ...
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FBGA* Pin Number A3P1000 Function E21 NC E22 IO84PDB1 IO215PDB3 F3 IO215NDB3 F4 IO224NDB3 F5 IO225NDB3 F6 VMV3 F7 IO11RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO25RSB0 F11 IO36RSB0 F12 IO42RSB0 F13 IO49RSB0 F14 IO56RSB0 F15 GBC0/IO72RSB0 ...
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Package Pin Assignments 484-Pin FBGA* Pin Number A3P1000 Function K19 IO88NDB1 K20 IO94NPB1 K21 IO98NDB1 K22 IO98PDB1 IO200PDB3 L3 IO210NPB3 L4 GFB0/IO208NPB3 L5 GFA0/IO207NDB3 L6 GFB1/IO208PPB3 L7 V COMPLF L8 GFC0/IO209NPB3 L10 GND L11 ...
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FBGA* Pin Number A3P1000 Function R17 GDB1/IO112PPB1 R18 GDC1/IO111PDB1 R19 IO107NDB1 R20 V CC R21 IO104NDB1 R22 IO105PDB1 T1 IO198PDB3 T2 IO198NDB3 IO194PPB3 T5 IO192PPB3 T6 GEC1/IO190PPB3 T7 IO192NPB3 T8 GNDQ T9 GEA2/IO187RSB2 T10 IO161RSB2 T11 ...
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Package Pin Assignments 484-Pin FBGA* Pin Number A3P1000 Function Y15 V CC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 V B1 CCI AA1 GND AA2 V B3 CCI AA3 NC AA4 IO181RSB2 AA5 IO178RSB2 ...
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... The QNG132 package was added to the table, "I/Os Per Package" Product Brief v1.1 and "Temperature Grade Packaging v1.1 Pin tables for A3P125 and A3P250 were added for the Changes indicates the status "Automotive ProASIC3 Product Family" table, "Automotive ProASIC3 Ordering Offerings". ...
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Datasheet Information Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "Automotive ...
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Actel is the leader in low power FPGAs and mixed signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court River Court,Meadows ...