SI3225-G-FQ Silicon Laboratories Inc, SI3225-G-FQ Datasheet
SI3225-G-FQ
Specifications of SI3225-G-FQ
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SI3225-G-FQ Summary of contents
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... ICs perform all high-voltage functions and operate from a 3 supply as well as single or dual battery supplies up to 100 V (Si3200) or 125 V (Si3202). The Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200/2 is available in a thermally-enhanced 16-pin small outline (SOIC) package. ...
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Si3220/25 Si3200/02 2 Rev. 1.3 ...
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Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . ...
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... On Si3200 revision E, the dv/dt of the voltage applied to the V 4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202 should be operated at a junction temperature below 140 °C for optimal reliability. ...
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... On Si3200 revision E, the dv/dt of the voltage applied to the V 4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202 should be operated at a junction temperature below 140 °C for optimal reliability. ...
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... Si3220/25 Si3200/02 Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Supply Voltage, Si3220/Si3225 Supply Voltage, Si3200/Si3202 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 High Battery Supply Voltage, Si3202 Low Battery Supply Voltage, Si3202 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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Table 3. 3.3 V Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current I DD ...
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Si3220/25 Si3200/02 Table 3. 3.3 V Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol Chipset Power P ...
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... Symbol V – V Supply I –I DD1 DD4 VDD1 Current (Si3220/Si3225) V Supply Current I DD VDD (Si3200/2) Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "3.14.4. Ringing Power Considerations" on page 54 for current and power consumption under other operating conditions ...
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Si3220/25 Si3200/02 Table Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current ...
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Table 5. AC Characteristics = ( – V 3. DD1 DD4 A Parameter Overload Level Overload Compression 1 Single Frequency Distortion Signal-to-(Noise + Distortion) 2 Ratio Audio Tone Generator Signal-to- 2 Distortion Ratio ...
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Si3220/25 Si3200/02 Table 5. AC Characteristics (Continued – V 3. DD1 DD4 A Parameter 6 Idle Channel Noise PSRR from V – V DD1 DD4 PSRR from V BAT Longitudinal to ...
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... ROTO RING LIM R TIP to ground TOTO THR THR Si3220, ac detection, VRING = 70 Vpk, no offset Si3220, dc detection offset Si3225, dc detection offset, R loop V Open circuit, V RING BATH 5 REN load, R LOOP V = 100 V BATH R THD 100 Hz Accuracy of ON/OFF times ↑CAL to ↓CAL bit Rev. 1.3 Min Typ ...
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Si3220/25 Si3200/02 Table 6. Linefeed Characteristics (Continued – V 3. DD1 DD4 A Parameter Loop Voltage Sense Accuracy Loop Current Sense Accuracy Power Alarm Threshold Accuracy Notes: 1. Adaptive linefeed is ...
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Table 8. Si3200/2 Characteristics = = (V 3. °C for K/F-Grade, – °C for B/G-Grade Parameter TIP/RING Pulldown Transistor Satura- tion Voltage TIP/RING Pullup Transistor Saturation Voltage Battery Switch ...
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Si3220/25 Si3200/02 Table 10. DC Characteristics ( – V 3. DD1 DD4 A Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage ...
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Table 12. Switching Characteristics—SPI ( – 3. DD1 DD4 A 1 Parameter 2 Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active Delay Time, ...
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Si3220/25 Si3200/02 Table 13. Switching Characteristics—PCM Highway Interface = ( – V 3. DD1 DD4 A Parameter PCLK Period Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance ...
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PCLK FSYNC DRX DTX Figure 2. PCM Highway Interface Timing Diagram Si3220/25 Si3200/ ...
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Si3220/25 Si3200/02 Table 14. Switching Characteristics—GCI Highway Serial Interface = ( – V 3. DD1 DD4 A 1 Parameter PCLK Period (2.048 MHz PCLK Mode) PCLK Period (4.096 MHz PCLK Mode) 2 FSYNC ...
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PCLK t su1 FSYNC Frame 0, DRX Bit DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR Si3220/25 Si3200/ ...
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Si3220/25 Si3200/02 Fundamental Output Power (dBm0) Figure 6. Overload Compression Performance 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 ...
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5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 ...
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Si3220/25 Si3200/02 1100 1000 900 800 700 600 500 400 300 200 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Figure 9. Transmit Group Delay Distortion 1100 1000 900 ...
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Si3220/25 Si3200/02 Rev. 1.3 25 ...
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Si3220/25 Si3200/02 26 Rev. 1.3 ...
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Si3220/25 Si3200/02 Rev. 1.3 27 ...
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Si3220/25 Si3200/02 2. Bill of Materials Table 15. Si3220 + Si3200 External Component Values Component Value C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac-sensing inputs. C3, C4, C13, C14 10 nF, 100 ...
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... R27, R28 Notes: 1. Optional. Only required when using dual-battery architecture. 2. Example power rating. 3. Required for Si3200 revision E only. 4. R27 and R28 must be populated for each Si3225 in the system. Si3220/25 Si3200/02 Value TIP/RING compensation capacitors. Low-pass filter capacitors to stabilize differential and com- mon mode SLIC feedback loops ...
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... The Si3220/Si3225 ICs also provide a variety of line monitoring and subscriber loop testing functions. All versions have the ability to generate specific dc and audio signals and continuously monitor and store all line voltage and current parameters ...
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... steps. The constant current region (defined by the loop current limit programmable from LIM 0.87 mA steps. The Si3220 and Si3225 exhibit a characteristic dc impedance of 640 Ω or 320 Ω during active mode. (See "3.4. Adaptive Linefeed" on page 34). is allowed to The TIP-RING voltage (V ...
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... TIP and RING. Sense resistor R DC RING; Capacitor C the TIP and RING leads to be measured. The Si3220 and Si3225 both use the Si3200/2 to drive TIP and with a RING and isolate the high-voltage line from the low- voltage CMOS devices. = –56 V and ...
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... Forward Active (LF[2:0] = 001). Linefeed is active, but audio paths are powered down until an off-hook condition is detected. The Si3220 and Si3225 automatically enter a low-power state to reduce power consumption during on-hook standby periods. Forward On-Hook Transmission (LF[2:0] = 010). Provides data transmission during an on-hook loop condition (e.g., transmitting FSK caller ID information between ringing bursts) ...
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... VOVRING V During Battery Tracking VOCTRACK OC 3.4. Adaptive Linefeed The Si3220/Si3225 features a proprietary dc feed design known as adaptive linefeed. Figure 16 shows the V/I characteristics of adaptive linefeed. Essentially, adaptive linefeed changes the source impedance of the dc feed as well as the apparent open-circuit voltage (VOC) in order to ensure the ability to source extended loop lengths ...
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... Figure 16. On the other hand, when the Si3220/Si3225 is used with a discrete bipolar transistor linefeed, the source impedance of the dc feed is 320 Ω both before and after the adaptive linefeed transition ...
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Si3220/25 Si3200/02 transition point. In the case of the discrete bipolar linefeed, since the source impedance is 320 Ω both before and after the adaptive linefeed transition, the V/I curve exhibits no discontinuity at the transition points when VOCDELTA = ...
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... Only one calibration should be necessary if the system remains powered up. To optimize Dual ProSLIC performance, the calibration routine in “AN58: Si3220/Si3225 Programmer’s Guide” should be followed. 3.7. Loop Voltage and Current Monitoring The Dual ProSLIC chipset continuously monitors the TIP and RING voltages and currents ...
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Si3220/25 Si3200/02 Table 21. Register and RAM Locations Used for Loop Monitoring Parameter Register/RAM Mnemonic Loop Voltage Sense VLOOP (V – TIP RING TIP Voltage Sense VTIP RING Voltage Sense VRING Loop Current Sense ILOOP Battery Voltage Sense ...
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... Note: The Si3200/2 THERM pin must be connected to the THERM a/b pin of the Si3220/Si3225 in order for the Si3200/2 power calculation method to work correctly. Si3220/25 Si3200/02 3.8.3. Power Filter and Alarms The power calculated during each A/D sample period must be filtered before being compared to a user- programmable maximum power threshold ...
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... Si3220/25 Si3200/02 When the THERM pin is connected from the Si3220 or Si3225 to the Si3200/2 (indicating the presence of an Si3200/2), the resolution of the PTH12 and PSUM RAM locations is modified from 498 µW/LSB to 1059.6 µW/ LSB. Additionally, the τ value must be modified THERMAL to accommodate the Si3200/2. For the Si3200/2, τ ...
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Table 22. Register and RAM Locations Used for Power Monitoring and Power Fault Detection Parameter Si3200/2 Total Power Output Monitor Si3200/2 Power Alarm Interrupt Pending Si3200/2 Power Alarm Interrupt Enable Q1/Q2 Power Alarm Threshold (discrete) Q1/Q2 Power Alarm Threshold (Si3200/2) ...
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... When using the Si3220, this mode should always be enabled to allow seamless switching between the ringing and off-hook states. The same switching scheme is used with the Si3225 to reduce power by switching to a lower off-hook battery when sourcing a short loop. Automatic battery selection should be disabled before using the manual battery select control bit (BSEL bit, Register 5— ...
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... Ringing Battery Switch (Si3220 only) Battery Select Indicator Battery Switching LPF *Note: Usable range for BATHTH and BATLTH is limited to the V SVBAT 806 kΩ V BLO V BHI Figure 19. External Battery Switching Using the Si3220/Si3225 Si3220/25 Si3200/02 Register/RAM Register/RAM Mnemonic Bits BATHTH BATHTH[14:7] BATLTH BATLTH[14:7] ...
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Si3220/25 Si3200/02 When generating a high-voltage ringing amplitude using the Si3220, the power dissipated during the OHT state typically increases due to operating from the ringing battery supply in this mode. To reduce power, the chipset provides the ability to ...
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Loop Closure Detection Loop closure detection is required to accurately signal a terminal device going off-hook during the Active, On- Hook Transmission (forward or reverse polarity), and ringing linefeed states. The functional blocks required to implement a loop closure ...
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Si3220/25 Si3200/02 Table 25. Register and RAM Locations Used for Loop Closure Detection Parameter Register/RAM Loop Closure Interrupt Pending Loop Closure Interrupt Enable Linefeed Shadow Loop Closure Detect Status Loop Closure Detect Debounce Interval Loop Current Sense Loop Closure Threshold ...
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The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LONGDBI. If the debounce interval is satisfied, the ...
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Si3220/25 Si3200/02 Table 27. State Transitions During Ground Key Detection # Loop State 1 LOOP OPEN 2 RING-GND 3 RING-GND (FWD-ACTIVE) 4 LOOP CLOSURE (FWD-ACTIVE) 5 LOOP OPEN (FWD-ACTIVE Input LONG Signal I Processor Q5 ...
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Table 28. Register and RAM Locations Used for Ground Key Detection Register/ Parameter Mnemonics Ground Key Interrupt Pending IRQVEC2 Ground Key Interrupt Enable Ground Key Linefeed Shadow LINEFEED Ground Key Detect Status LCRRTP Ground Key Detect Debounce LONGDBI Interval Longitudinal ...
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Si3220/25 Si3200/02 3.12. Ringing Generation ® The Si3220-based Dual ProSLIC balanced ringing waveform with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both ...
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... VRNGNG Voltage Sense External Ringing Generator IRNGNG Current Sense Ringing Initial Phase RINGPHAS Sinusoidal Trapezoid External Ringing Ringing Relay Driver Enable RELAYCON (Si3225 only) Ringing Overhead Voltage VOVRING Ringing Speedup Timer SPEEDUPR Si3220/25 Si3200/02 Register/RAM Bits TRAP Sinusoid/Trapezoid TAEN Enabled/Disabled TIEN ...
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Si3220/25 Si3200/02 3.12.1. Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by the on- chip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies ...
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V RING Si3220 DC Offset GND V TIP DC Offset V OFF -80V V RING V BATR Figure 25. Internal Unbalanced Ringing To enable unbalanced ringing, set the RINGUNB bit of the RINGCON register. As with internal balanced ringing, the ...
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... Therefore ring trip detection scheme is required when sourcing longer loop lengths. The Si3220 can implement either dc-based ring trip detection scheme depending on the application. The Si3225 allows external dc ring trip detection when using modification a battery-backed monitoring the ringing feed path through two sensing inputs on each channel ...
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Ringtrip Timeout Counter The Dual ProSLIC incorporates a ringtrip timeout counter, RTCOUNT, that will monitor the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter a sufficient amount of time (RTCOUNT ...
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... Internal Yes (Si3220) 33– 16–32 Hz Yes External (Si3225) 33–60 Hz Yes Notes: 1. All calculated values should be rounded to the nearest integer. 2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations. Table 31. Register and RAM Locations Used for Ring Trip Detection Parameter Ring Trip Interrupt Pending ...
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... Test relay drivers TRD1a, TRD1b, TRD2a, and TRD2b are provided in all product versions, and ringing relay drivers RRDa and RRDb are included for the Si3225 only. In most applications, the relay can be driven directly from the Dual ProSLIC with no external relay drive circuitry required. Figure 28 illustrates the internal relay driver circuitry using relay ...
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... Si3220/25 Si3200/02 Si3220/ Si3225 Figure 29. Driving Relays with V The maximum allowable R value can be calculated with the following equation: DRV MaxR DRV Table 32. Recommended R ProSLIC V Relay V DD 3.3 V ±5% 3.3 V ± ± ±5% 3.3 V ± ±5% 3.3 V ± ±10% 3.3 V ± ±10% 3.3 V ± ...
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Si3220/25 Si3200/02 Rev. 1.3 59 ...
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... By observing the phase of the ringing signal and constantly monitoring the open-circuit T-R voltage, V Si3225 can detect the next time when there is zero voltage across the relay contacts. 3.16.3. Opening the Relay at Zero Current Opening the ringing relay at zero current also is ...
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Setting the linefeed register to the opposite polarity immediately reverses (hard reversal) the line polarity. For example, to transition from Forward Active mode to Reverse Active mode changes LF[2:0] from 001 to 101. Polarity reversal is accommodated in the OHT ...
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Si3220/25 Si3200/02 3.18. Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop thus minimizing the receive path signal reflected back onto the transmit ...
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ON, the IIR filter experiences a discontinuity in the input signal. By writing power-down register 124 (decimal) with 0xC0, the clocks to the digital synthesis filter are forced to be continuously ON at all times, and ...
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Si3220/25 Si3200/02 8 kHz Clock OSCnEN Zero 16-Bit Cross Modulo OSCnTA Logic Expire Counter OSCnTI Expire OSCnTA OSCnTAEN OSCnTI OSCnTIEN *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively 3.20.2. Oscillator Frequency and ...
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To enable automatic cadence for tone generator 1, define the OSC1TA and OSC1TI registers and set the OSC1TAEN and OSC1TIEN bits. This enables each of the timers to control the state of the oscillator enable bit, OSC1EN. The 16-bit counter ...
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Si3220/25 Si3200/02 OSC1EN ... ... 0,1 , OSC1TA ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Message Parameter 1 Type Length Message Header Parameter Type Figure 37. On-Hook Caller ID Transmission Sequence ...
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Tone Generator Interrupts Both the active and inactive timers can generate an interrupt to signal “on/off” transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the OS1TAE and OS1TIE bits. Timer ...
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Si3220/25 Si3200/02 3.22. Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm ...
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... Figure 38. Pulse Metering Generation Block Diagram 3.23. DTMF Detection On-chip DTMF detection, also known as touch tone, is available in the Si3220 and Si3225 in-band signaling system that replaces the pulse- dial signaling standard. In DTMF, two tones generate a DTMF digit. One tone is chosen from the four possible row tones, and one tone is chosen from the four possible column tones ...
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Si3220/25 Si3200/02 Table 40 outlines the hex codes corresponding to the detected DTMF digits. Table 40. DTMF Hex Codes Digit Hex code 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 7 0x7 8 0x8 9 0x9 ...
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A/D converter. One more digital filter, THPF, is available in the transmit path. THPF implements the high-pass attenuation requirements for signals below 65 Hz. ...
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Si3220/25 Si3200/02 The receive path transfer function requirement, shown in Figure 8 on page 23, is very similar to the transmit path transfer function. The PCM data rate is 8 kHz; so, no frequencies greater than 4 kHz are digitally-encoded ...
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Interrupt Logic The Dual ProSLIC devices are capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Ground Key detected Power alarm DTMF digit detected Active timer 1 expired Inactive timer 1 expired Active ...
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Si3220/25 Si3200/02 The control byte has the following structure and is presented on the SDI pin MSB first BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3] See Table 42 for bit definitions. 7 BRDCST Indicates a broadcast operation ...
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SDO CS CPU SDI SPI Clock Figure 41. SPI Daisy-Chain Mode Rev. 1.3 Si3220/25 Si3200/02 SDI0 SDI Channel 0 CS SDI1 Dual ProSLIC #1 SDO Channel 1 SCLK SDITHRU SDI2 SDI Channel 2 CS SDI3 Dual ProSLIC #2 SDO Channel ...
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Si3220/25 Si3200/02 In Figure 42, the CID field is zero. As this field is decremented (in LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control ...
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Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data ...
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Si3220/25 Si3200/02 CS SCLK SDI CONTROL SDO Figure 47. RAM Write Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 48. RAM Read Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 49. RAM ...
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PCM Interface The Dual ProSLIC devices programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the PCLK and FSYNC inputs, PCM Mode Select, PCM Transmit Start PCMTXLO), and PCM Receive Start ...
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Si3220/25 Si3200/02 PCLK FSYNC PCLK_CNT 0 1 DRX MSB DTX HI-Z MSB Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0) PCLK FSYNC PCLK_CNT 0 1 DRX DTX HI-Z Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS ...
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PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC Si3220/25 Si3200/ Rev. 1.3 ...
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Si3220/25 Si3200/02 Table 43. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Table 44. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: ...
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Si3220/25 Si3200/02 3.31. General Circuit Interface The Dual ProSLIC devices also contain an alternate communication interface to the SPI and PCM control and data interface. The general circuit interface (GCI) is used for the transmission and reception of both control ...
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MR and MX. The C/I bits indicate status and command communication handshaking bits Monitor Receive, MR, and Monitor Transmit, MX, exchange data in the Monitor channel. Figure 55 illustrates the contents of a GCI highway frame. 3.31.1. 16-Bit ...
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Si3220/25 Si3200/02 FS CH0 Sub-Frame 16 B1 Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode 1st Byte MX Transm itter MX MR Receiver MR Figure 57. Monitor Handshake Timing 86 125 µ Frame CH1 CH2 8 ...
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The Idle state is achieved by the MX and MR bits being held inactive for two or more frames. When a transmission is initiated by a host device, an active state is seen on the downstream MX bit. This signals ...
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Si3220/25 Si3200/02 Idle Rec eiv alid New ...
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Idle RQT RQT RQT nth ...
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Si3220/25 Si3200/02 Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver ...
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Monitor Data Downstream $01 $FF $FF $91 $91 125 µs 1 Frame MX Downstream Bit MR Downstream Bit Monitor Data Upstream $FF $FF $FF $FF $FF MX Upstream Bit MR Upstream Bit = Acknowledgement of data reception Figure 61. Example ...
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Si3220/25 Si3200/02 3.31.3. Programming the Dual ProSLIC Using the Monitor Channel The Dual ProSLIC devices use the monitor channel to Transfer status or operating mode information to and from the host processor. Communication with the Dual ProSLIC should be in ...
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This section defines the functionality of the six C/I bits whether they are being transmitted to the GCI bus via the DTX pin (upstream) or received from the GCI bus via the DRX pin (downstream). The structure ...
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Si3220/25 Si3200/02 Receive New C/I Code = P? No Store in S Receive New C/I Code = Figure 63. Protocol for Receiving C/I Bits in the Dual ProSLIC When the Dual ProSLIC is set to ...
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If this problem persists after the power alarm settings are verified, a system fault is probable, and the user should take measures to diagnose the problem. 3.31.10. Upstream (Transmit) SC Channel Byte The upstream SC channel ...
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Si3220/25 Si3200/02 The interrupt information for channels A and single bit that indicates that one or more interrupts might exist on the respective channel. Each of the individual interrupt flags (see registers 18–20) can be individually masked ...
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... REN without causing the terminal equipment to ring audibly. This ringing signal can be either balanced or unbalanced depending on the state of the RINGUNB bit of the RINGCON register. This feature is also available with the Si3225 provided that sufficient battery voltage is present. Rev. 1.3 Comments — ...
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... I = ringing current when using an external RING,EXT ringing source (Si3225 only) The SLIC diagnostic capability consists of a peak detect block and two filter blocks, one for dc and one for ac. The topology is illustrated in Figure 64. The peak detect filter block reports the magnitude of the largest positive or negative value without sign ...
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Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on and off times of the ringing and pulse-metering signals. The tone generation oscillator can be used to program a time period for averaging specific measured ...
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Si3220/25 Si3200/02 Line capacitance measurement. Implemented like the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized two-wire impedance of the Dual ProSLIC, the roll-off effect can ...
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... Capacitor used in low-pass filter to stabilize SLIC feedback loops. Component Reference Ground. Return path for differential and common-mode capacitors. Do not connect to system ground. Rev. 1 RRDa SDITHRU 45 SDI 44 SDO 43 SCLK Si3225 42 VDD4 41 GND4 64-Lead TQFP 40 INT (epad) 39 PCLK 38 GND3 37 VDD3 36 DTX 35 DRX 34 FSYNC 33 RESET ...
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... Si3220/25 Si3200/02 Symbol Pin Number(s) Si3220 Si3225 9 9 IREF 17, 64 17, 64 STIPDCb, STIPDCa 18, 63 18, 63 STIPACb, STI- PACa 19, 62 19, 62 SRINGACb, SRINGACa 20, 61 20, 61 SRINGDCb, SRINGDCa 21, 60 21, 60 ITIPNb, ITIPNa 22, 59 22, 59 IRINGNb, IRINGNa 23, 58 23, 58 ITIPPb, ITIPPa 24, 37, 24, 37 DD2 ...
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... Symbol Pin Number(s) Si3220 Si3225 28, 52 28, 52 RTRPb, RTRPa 30, 50 30, 50 TRD2b, TRD2a 31, 48 RRDb, RRDa 31, 48 GPOb, GPOa 32, 49 32, 49 BATSELb, BATSELa 35 35 DRX 36 36 DTX 39 39 PCLK 33 33 RESET 34 34 FSYNC 40 40 INT 43 43 SCLK 44 44 SDO 45 45 SDI ...
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... Si3220/25 Si3200/02 Symbol Pin Number(s) Si3220 Si3225 46 46 SDITHRU BLKRNG epad epad GND 104 Input/ Description Output O Serial Data Daisy Chain. Enables multiple devices to use a single CS for serial port con- trol. Connect SDITHRU pin from master device to SDI pin of slave device. An internal pullup resistor holds this pin high dur- ing idle periods ...
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... Main power supply for all internal circuitry. Connect supply. Decouple locally with a 0.1 µF/10 V capacitor. Battery Voltage Select. Connect to the BATSEL pin of the Si3220 or Si3225 through an external resistor to enable automatic battery switching. No connection is required when used with the Si3225 in a single battery system configuration. ...
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... Connect to the IRINGP lead of the Si3220 or Si3225. Thermal Sensor. Connect to THERM pin of Si3220 or Si3225. Negative TIP Current Control. Connect to the ITIPN lead of the Si3220 or Si3225. Positive TIP Current Control. Connect to the ITIPP lead of the Si3220 or Si3225. Exposed Die Paddle Ground. For adequate thermal management, the exposed die paddle should be sol- dered to a PCB pad that is connected to low-impedance inner and/or back- side ground planes using multiple vias. See “ ...
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Package Outline: 64-Pin TQFP Figure 65 illustrates the package details for the Dual ProSLIC. Table 53 lists the values for the dimensions shown in the illustration. Symbol Millimeters Min Nom A — — A1 0.05 — A2 0.95 1.00 ...
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Si3220/25 Si3200/02 7. Package Outline: 16-Pin ESOIC Figure 66 illustrates the package details for the Si3200/2. Table 54 lists the values for the dimensions shown in the illustration Seating Plane Figure 66. 16-Pin ...
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... Si3220/Si3225 System Demonstration Kit User's Guide” “AN74: SiLINKPS-EVB User's Guide” “AN75: Si322x Dual ProSLIC Demo PBX and GR-909 Testing Software Guide” “AN86: Ringing / Ringtrip Operation and Architecture on the Si3220/Si3225” “AN88: Dual ProSLIC Line Card Design” “AN91: Si3200 Power Offload Circuit” ...
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... Si3220DC0-EVB Si3225PPT0-EVB Si3225DC0-EVB 110 On-Chip External Pulse Ringing Ringing Metering Support Description ProSLIC Si3220 Eval Board, Daughter Card Si3220 Daughter Card Only Si3225 Eval Board, Daughter Card Si3225 Daughter Card Only Rev. 1.3 Lead-Free/ Temp Range Package RoHS Compliant SOIC-16 o – ...
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OCUMENT HANGE IST Revision 1.1 to Revision 1.2 Updated power supply characteristics in Table 3 and Table 4. Added note to Tables 15 and 17 to clarify SDO and DTX pulldown requirements when multiple Si3220/25s are connected ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...