SI3225-GQ Silicon Laboratories Inc, SI3225-GQ Datasheet

IC SLIC/CODEC DUAL-CH 64TQFP

SI3225-GQ

Manufacturer Part Number
SI3225-GQ
Description
IC SLIC/CODEC DUAL-CH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets

Specifications of SI3225-GQ

Package / Case
*
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
65mA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Product
SLIC
Supply Voltage (min)
3.13 V
Supply Current
22 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Channels
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3225-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
D
Features
Applications
Description
The Dual ProSLIC
SLIC and codec functionality into a single IC to provide a complete dual-channel
analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI
specifications. The Si3220 includes internal ringing generation to eliminate
centralized ringers and ringing relays, and the Si3225 supports centralized ringing
for long loop and legacy applications. On-chip subscriber loop and audio testing
allows remote diagnostics and fault detection with no external test equipment or
relays. The Si3220 and Si3225 operate from a single 3.3 V or 5 V supply and
interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed
interface IC performs all high-voltage functions and operates from a 3.3 V or 5 V
supply as well as single or dual battery supplies up to 100 V. The Si3220 and
Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is
available in a thermally-enhanced 16-pin small outline (SOIC) package.
Functional Block Diagram
Rev. 1.0 6/04
FSYNC
SCLK
PCLK
Performs all BORSCHT functions
Ideal for applications up to 18 kft
Internal balanced ringing to 65 V
(Si3220)
External bulk ringer support (Si3225)
Low standby power consumption:
<70 mW per channel
Software-programmable parameters:
Automatic switching of up to three battery
supplies
Digital loop carriers
Central Office telephony
Pair gain remote terminals
Wireless local loop
U A L
SDO
DRX
DTX
SDI
CS
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Ringing frequency, amplitude, cadence,
and waveshape (Si3220)
Two-wire ac impedance
Transhybrid balance
DC current loop feed (18–45 mA)
Loop closure and ring trip thresholds
Ground key detect threshold
INT RESET
Interface
Interface
Control
PCM /
GCI
PLL
P
SPI
R O
®
is a series of low-voltage CMOS devices that integrate both
Subscriber Line
& Ring Trip
Pulse Metering
Programmable
Generator
S LI C
Modem Tone
Audio Filters
Diagnostics
Ringing
Generators
Sense
Dual Tone
Detection
Si3220/25
DSP
Hybrid Balance
DTMF Decode
Loop Closure,
& Ground Key
Relay Drivers
Gain Adjust
Impedance
2-Wire AC
Detection
Caller ID
®
rms
FSK
text
P
Copyright © 2004 by Silicon Laboratories
Private Branch Exchange (PBX) systems
Cable telephony
Voice over IP/voice over DSL
ISDN terminal adapters
R O G R A M M A B L E
Codec A
Codec B
DAC
ADC
DAC
ADC
On-hook transmission
Loop or ground start operation with
smooth/abrupt polarity reversal
Modem/fax tone detection
DTMF generation/decoding
Dual tone generators
A-Law/µ-Law, linear PCM
companding
PCM and SPI bus digital interfaces
with programmable interrupts
GCI/IOM-2 mode support
3.3 or 5 V operation
GR-909 loop diagnostics
Audio diagnostics with loopback
12 kHz/16 kHz pulse metering
(Si3220)
FSK caller ID generation
SLIC B
SLIC A
Linefeed
Linefeed
Linefeed
Linefeed
Control
Monitor
Control
Monitor
Linefeed
Interface
Linefeed
Interface
Si3200
Si3200
S i 3 2 2 0 / S i 3 2 2 5
Channel A
Channel B
RING
RING
TIP
TIP
C M O S S L I C / C
Patents pending
See "Dual ProSLIC® Selection
Part Number
Si3220
Si3225
Ordering Information
Guide" on page 2.
Ringing
External
Method
Internal
Ringer
Si3220/Si3225
O D E C

Related parts for SI3225-GQ

SI3225-GQ Summary of contents

Page 1

... On-chip subscriber loop and audio testing allows remote diagnostics and fault detection with no external test equipment or relays. The Si3220 and Si3225 operate from a single 3 supply and interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed interface IC performs all high-voltage functions and operates from a 3 ...

Page 2

... Part Description Number Si3200-KS Linefeed interface Si3200-BS Linefeed interface Si3200-FS Linefeed interface Si3200-GS Linefeed interface Si3220-FQ Dual ProSLIC Si3220-GQ Dual ProSLIC Si3225-FQ Dual ProSLIC Si3225-GQ Dual ProSLIC 2 On-Chip External Pulse Ringing Ringing Metering Support Rev. 1.0 Lead Temp Package Free Range o ...

Page 3

... General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Pin Descriptions: Si3220/ Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Related Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Si3220/Si3225 Rev. 1.0 Page 3 ...

Page 4

... Si3220/Si3225 Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter Supply Voltage, Si3200 and Si3220/Si3225 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 TIP or RING Voltage, Si3205 TIP, RING Current, Si3200 STIPAC, STIPDC, SRINGAC, SRINGDC Current, Si3220/Si3225 Input Current, Digital Input Pins ...

Page 5

... Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Supply Voltage, Si3220/Si3225 Supply Voltage, Si3200 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Table 3 ...

Page 6

... Si3220/Si3225 Table 3. 3.3 V Power Supply Characteristics = = ( –V 3 °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V Supply Cur VDD rent (Si3200) V Supply Cur- I BAT VBAT rent (Si3200) Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. ...

Page 7

... ABIAS = 4 mA –48 V BAT Forward/reverse OHT, OBIAS = 4 mA –48 V BAT Forward/reverse OHT, OBIAS = 4 mA –70 V BAT Ringing RING rms – REN load BAT term. Rev. 1.0 Si3220/Si3225 Min Typ Max Unit — 8 — mW — 65 — mW — 70 — mW — 80 — mW — 240 — ...

Page 8

... Symbol V –V Supply I –I DD1 DD4 VDD1 Current (Si3220/Si3225) V Supply Current I DD VDD (Si3200) Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "Ringing Power Considerations" on page 50 for current and power consumption under other operating conditions. ...

Page 9

... BAT Forward/reverse OHT, OBIAS = 4 mA –48 V BAT Forward/reverse OHT, OBIAS = 4 mA –70 V BAT Ringing RING rms V = – REN load BAT term. Rev. 1.0 Si3220/Si3225 Min Typ Max — 100 — = –70 V — 225 — = –70 V — 400 — — 4.4 + — ...

Page 10

... Si3220/Si3225 Table 5. AC Characteristics = ( –V 3. °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Overload Level Overload Compression 1 Single Frequency Distortion Signal-to-(Noise + Distortion) 2 Ratio Audio Tone Generator Signal-to- 2 Distortion Ratio Intermodulation Distortion 2 Gain Accuracy Attenuation Distortion vs. Freq. ...

Page 11

... Active off-hook 200 Hz to 3.4 kHz Register-dependent OBIAS/ABIAS – Assumes ideal line impedance matching. RING = 600 Ω 600 Ω synthesized using RS register L S Rev. 1.0 Si3220/Si3225 Min Typ Max Unit 34 40 — dB — dBrnC — –78 –75 dBmP — — 18 dBrn 40 — ...

Page 12

... ROTO RING LIM R TIP to ground TOTO THR THR Si3220, ac detection, VRING = 70 Vpk, no offset 80mA TH Si3220, dc detection offset, I Si3225, dc detection offset, R loop V Open circuit, V RING BATH 5 REN load, R LOOP V = 100 V BATH R THD 100 Hz Accuracy of ON/OFF times ↑CAL to ↓CAL bit Rev. 1.0 Min ...

Page 13

... ABIAS V GND – V (Forward) CM TIP GND – V (Reverse) RING LIM LIM R (V – V )/I SAT BAT BATH OUT Rev. 1.0 Si3220/Si3225 Min Typ Max — ±2 ± — ±7 ±10 — — ± LOOP DC,MAX Min Typ Max — 8 — –1.0 ± ...

Page 14

... Si3220/Si3225 Table 8. Si3200 Characteristics (Continued 3. °C for K/F-Grade, – °C for B/G-Grade Parameter OPEN State TIP/RING Leakage Current Internal Blocking Diode Forward Voltage Notes 600 Ω 2 LOAD OUT Table 9. DC Characteristics ( – DD1 DD4 Parameter Symbol High Level Input ...

Page 15

... V OUT DD1 DD4 IO < – DD1 DD4 IO < °C for K/F-Grade, – °C for B/G-Grade, C Symbol Min t — 500 Rev. 1.0 Si3220/Si3225 Min Typ Max Unit 0 — 5. — — 0 – 0.6 — — — — 0.4 V — — 0. — ...

Page 16

... Si3220/Si3225 Table 12. Switching Characteristics—SPI 3. °C for K/F-Grade, – °C for B/G-Grade, C DDA DDA A Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active Delay Time, SCLK Fall to SDO Transition Delay Time, CS Rise to SDO Tri-state ...

Page 17

... K/F-Grade, – °C for B/G-Grade, C Symbol Test Conditions dty t jitter su1 su2 wfs Rev. 1.0 Si3220/Si3225 = 20 pF Units Min Typ Max 122 — 3906 — 256 — — 512 — — 768 — — 1.024 — MHz — 1.536 — MHz — 1.544 — ...

Page 18

... Si3220/Si3225 PCLK FSYNC DRX DTX Figure 2. PCM Highway Interface Timing Diagram Rev. 1 ...

Page 19

... Conditions dty t jitter su1 su2 wfs su2 Frame 0, Bit 0 Rev. 1.0 Si3220/Si3225 Min Typ Max Units — 488 — ns — 244 — ns µ s — 125 — — — ±120 ns — — — — — — — — — — — — — ...

Page 20

... Si3220/Si3225 PCLK t su1 FSYNC Frame 0, DRX Bit 0 DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR su2 Frame 0, Bit 0 Rev. 1 ...

Page 21

... Figure 7. Transmit Path Frequency Response Acceptable Region Fundamental Input Power (dBm0) TX Attenuation Distortion Frequency (Hz) TX Pass−Band Detail Frequency (Hz) Rev. 1.0 Si3220/Si3225 21 ...

Page 22

... Si3220/Si3225 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 −1.2 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 Figure 8 ...

Page 23

... RX Group Delay Distortion 1100 1000 900 800 700 600 500 400 300 200 Typical Response 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Frequency (Hz) Figure 10. Receive Group Delay Distortion Si3220/Si3225 Rev. 1.0 23 ...

Page 24

... Si3220/Si3225 24 Rev. 1.0 ...

Page 25

... BATSELa 49 TRD2a 50 TRD1a THERMa 54 IRINGPa 55 GND1 56 VDD1 57 ITIPPa 58 IRINGNa 59 ITIPNa 60 SRINGDCa 61 SRINGACa 62 STIPACa 63 STIPDCa Si3220/Si3225 BATSELb 32 GPOb 31 TRD2b 30 TRD1b THERMb 27 IRINGPb 26 GND2 25 VDD2 24 ITIPPb 23 IRINGNb 22 ITIPNb 21 SRINGDCb 20 SRINGACb 19 STIPACb 18 STIPDCb Rev. 1.0 25 ...

Page 26

... Si3220/Si3225 BATSELa 49 TRD2a 50 TRD1a 51 RTRPa 52 BLKRNG 53 THERMa 54 IRINGPa 55 GND1 56 VDD1 57 ITIPPa 58 IRINGNa 59 ITIPNa 60 SRINGDCa 61 SRINGACa 62 STIPACa 63 STIPDCa BATSELb 32 RRDb 31 TRD2b 30 TRD1b 29 RTRPb 28 THERMb 27 IRINGPb 26 GND2 25 VDD2 24 ITIPPb 23 IRINGNb 22 ITIPNb 21 SRINGDCb 20 SRINGACb 19 STIPACb 18 STIPDCb Rev. 1.0 1 ...

Page 27

... R20, R22 15 Ω , 1/8 W, ±5% R21, R23 39 k Ω , 1/10 W, ±5% R24, R25 Table 16. Si3225 + Si3200 External Component Values Component C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inputs. C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% 1 µ ...

Page 28

... The Si3220/Si3225 ICs also provide a variety of line monitoring and subscriber loop testing functions. All versions have the ability to generate specific dc and audio signals and continuously monitor and store all line voltage and current parameters ...

Page 29

... R DC RING; Capacitor C the TIP and RING leads to be measured. The Si3220 and Si3225 both use the Si3200 to drive TIP and RING and isolate the high-voltage line from the low-voltage CMOS devices. The Si3220 and Si3225 measure voltage at various nodes to monitor the linefeed current. R provide these measuring points ...

Page 30

... Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads (Diagram Illustrates either TIP or RING Lead of a Single Channel) 30 Low Frequency Diagnostic Filters Monitor A/D A/D DSP D/A SLIC DAC Σ SLIC Control SLIC Control Loop Si3200 Battery Current Select Mirror Control Rev. 1.0 Si3220/ Si3225 V Sense BAT R BAT ...

Page 31

... Forward Active (LF[2:0] = 001). Linefeed is active, but audio paths are powered down until an off-hook condition is detected. The Si3220 and Si3225 automatically enter a low-power state to reduce power consumption during on-hook standby periods. Forward On-Hook Transmission (LF[2:0] = 010). Provides data transmission during an on-hook loop condition (e.g., transmitting FSK caller ID information between ringing bursts) ...

Page 32

... VOVRING V During Battery Tracking VOCTRACK OC Adaptive Linefeed The Si3220/Si3225 features a proprietary dc feed design known as adaptive linefeed. Figure 16 shows the V/I characteristics of adaptive linefeed. Essentially, adaptive linefeed changes the source impedance of the dc feed as well as the apparent open-circuit voltage (VOC) in order to ensure the ability to source extended loop lengths. The following sections provide a detailed explanation of adaptive linefeed ...

Page 33

... Figure 16. On the other hand, when the Si3220/Si3225 is used with a discrete bipolar transistor linefeed the source impedance of the dc feed is 320 Ω both before and after the adaptive linefeed transition ...

Page 34

... Si3220/Si3225 VOC voltage boost associated with a non-zero VOCDELTA value. With VOCDELTA = 0 in the case of the Si3200, the adaptive linefeed transition still changes the source impedance from 640 Ω to 320 Ω , and there is a corresponding discontinuity at the transition point. In the case of the discrete bipolar linefeed, since the source impedance is 320 Ω ...

Page 35

... Only one calibration should be necessary if the system remains powered up. To optimize Dual ProSLIC performance, the calibration routine in “AN58: Si3220/Si3225 Programmer’s Guide” should be followed. Loop Voltage and Current Monitoring The Dual ProSLIC chipset continuously monitors the TIP and RING voltages and currents ...

Page 36

... Si3220/Si3225 Table 20. Register and RAM Locations Used for Loop Monitoring Parameter Register/RAM Mnemonic Loop Voltage Sense VLOOP (V – TIP RING TIP Voltage Sense VTIP RING Voltage Sense VRING Loop Current Sense ILOOP Battery Voltage Sense VBAT Longitudinal Current ILONG Sense External Ringing Gen- ...

Page 37

... Note: The Si3200 THERM pin must be connected to the THERM a/b pin of the Si3220/Si3225 in order for the Si3200 power calculation method to work correctly. Power Filter and Alarms The power calculated during each A/D sample period must be filtered before being compared to a user- programmable maximum power threshold ...

Page 38

... Si3220/Si3225 When the THERM pin is connected from the Si3220 or Si3225 to the Si3200 (indicating the presence of an Si3200), the resolution of the PTH12 and PSUM RAM locations is modified from 498 µ W/LSB to 1059.6 µ W/ LSB. Additionally, the τ value must be modified THERMAL to accommodate the Si3200. For the Si3200, τ ...

Page 39

... SLIC chipset, often resulting in thermal shutdown or destruction of the device due to thermal runaway. A special power offload circuit is recommended for applications. Refer to “AN91: Si3200 Power Off-load Circuit” for power offload circuit usage guidelines. Rev. 1.0 Si3220/Si3225 Resolution Range 1059.6 µ 34.72 W N/A N/A N/A N/A 498 µ ...

Page 40

... When using the Si3220, this mode should always be enabled to allow seamless switching between the ringing and off-hook states. The same switching scheme is used with the Si3225 to reduce power by switching to a lower off-hook battery when sourcing a short loop. Two thresholds are provided to enable battery switching with hysteresis ...

Page 41

... The Si3220’s BATSEL pin is used to switch between the V (typically –48 V) and V BHI BLO 806 kΩ V BLO V BHI Figure 19. External Battery Switching Using the Si3220/Si3225 0.1 µF V BRING 0.1 µF V BLO V BHI Figure 20. 3-Battery Switching with Si3220/Si3200 –24 V) rails using the switch internal to the Si3200. The Si3220’ ...

Page 42

... Si3220/Si3225 Table 23. Three-Battery Switching Components Component Value D1 200 V, 200 mA Q1 100 V PNP Q2 100 V NPN R101 1/10 W, ± Ω ,1/10 W, ± 5% R102 402 k Ω ,1/10 W,± 1% R103 Loop Closure Detection Loop closure detection is required to accurately signal a terminal device going off-hook during the Active, On- Hook Transmission (forward or reverse polarity), and ringing linefeed states ...

Page 43

... Where f = the desired cutoff frequency of the filter. The programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). A typical value of 10 (0A10h) is sufficient to filter out any unwanted ac LONG artifacts while allowing the dc information to pass through the filter. Rev. 1.0 Si3220/Si3225 Programmable LSB Effective Range Size Resolution Yes/No ...

Page 44

... Si3220/Si3225 The output of the low-pass filter is compared to the programmable threshold, LONGHITH. Hysteresis is enabled by programming a LONGLOTH, to detect when the ground key is released. The threshold comparator output feeds a programmable debounce filter. The output of the debounce filter remains in its present state unless the input remains in ...

Page 45

... Yes/No LFS[2:0] Monitor only LONGHI Monitor only LONGDBI[15: 40.96 s ILONG[15:0] Monitor only LONG- HITH[15:0] 101.09 mA* LON- GLOTH[15:0] 101.09 mA* LONGLPF[15: 4000h Rev. 1.0 Si3220/Si3225 LONGHI Filter Interrupt LONGS Logic LONGE LSB Resolution Size N/A N/A N/A N/A N/A N/A N/A N/A 1. ...

Page 46

... Si3220/Si3225 Ringing Generation The Si3220-based Dual ProSLIC chipset provides a balanced ringing waveform with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and the RING lines using ringing waveforms that are 180° ...

Page 47

... VRNGNG Voltage Sense External Ringing Generator IRNGNG Current Sense Ringing Initial Phase RINGPHAS Sinusoidal Trapezoid External Ringing Ringing Relay Driver Enable RELAYCON (Si3225 only) Ringing Overhead Voltage VOVRING Ringing Speedup Timer SPEEDUPR Register/RAM Bits TRAP Sinusoid/Trapezoid TAEN Enabled/Disabled TIEN Enabled/Disabled RINGEN ...

Page 48

... Si3220/Si3225 Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by the on- chip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated kHz rate ...

Page 49

... Figure 26. Trapezoidal Ringing Waveform Ringing DC Offset Voltage A dc offset voltage can be added to the Si3220’s ac ringing waveform by programming the RINGOF RAM location to the appropriate setting. The value RINGOF is calculated as follows: OVRING Rev. 1.0 Si3220/Si3225 the register values V OFF T = 1/freq t time RISE ...

Page 50

... The Si3220 can implement either dc-based ring trip detection scheme depending on the application. The Si3225 allows external dc ring trip detection when using a battery-backed monitoring the ringing feed path through two sensing modification inputs on each channel. By monitoring this path, the Dual ProSLIC detects a dc current flowing in the loop once the end equipment has gone off-hook ...

Page 51

... The ac and dc ring trip debounce intervals can be calculated based on the following equations: RTACDB = t debounce RTDCDB = t debounce RTACTH AC Ring Trip Threshold _ Debounce Filter_AC Digital + LPF RTACDB RTPER Digital + LPF _ DC Ring Trip Threshold RTDCTH Rev. 1.0 Si3220/Si3225 (1600/RTPER) (1600/RTPER) RTP Interrupt RTRIPS Logic RTRIPE Debounce Filter_DC RTDCDB 51 ...

Page 52

... Internal Yes (Si3220) 33– External 16–32 Hz Yes (Si3225) 33–60 Hz Yes Notes: 1. All calculated values should be rounded to the nearest integer. 2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations. Table 30. Register and RAM Locations Used for Ring Trip Detection Parameter Ring Trip Interrupt Pending ...

Page 53

... Test relay drivers TRD1a, TRD1b, TRD2a, and TRD2b are provided in all product versions, and ringing relay drivers RRDa and RRDb are included for the Si3225 only. In most applications, the relay can be driven directly from the Dual ProSLIC with no external relay drive circuitry required. Figure 28 illustrates the internal relay driver circuitry using relay ...

Page 54

... Si3220/Si3225 Si3220/ Si3225 Figure 29. Driving Relays with V The maximum allowable R MaxR DRV Table 31. Recommended R ProSLIC V Relay V DD 3.3 V ±5% 3.3 V ± ± ±5% 3.3 V ± ±5% 3.3 V ± ±10% 3.3 V ± ±10% 3.3 V ± ±10 ± ±10 ± ±10 ± ±10% ...

Page 55

... Si3220/Si3225 Rev. 1.0 55 ...

Page 56

... By observing the phase of the ringing signal and constantly monitoring the open-circuit T-R voltage, V Si3225 can detect the next time when there is zero voltage across the relay contacts. Opening the Relay at Zero Current Opening the ringing relay at zero current also is ...

Page 57

... Read only 1 = Ramp Return to previous Disabled 1 = Enabled V/1. V/1.25 ms Set VOCZERO bit 2V/1.25ms slope set by RAMP bit Rev. 1.0 Si3220/Si3225 ) to 1 followed by a return to the original Register/RAM Register/RAM Bits Mnemonic LF[2:0] LINEFEED POLREV POLREV VOCZERO POLREV PREN POLREV RAMP POLREV 70 80 ...

Page 58

... Si3220/Si3225 Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop to minimize the receive path signal reflected back onto the transmit path. The Dual ProSLIC chipset provides on- chip digitally-programmable, two-wire synthesis to meet return loss requirements against virtually any global two-wire impedance requirement ...

Page 59

... Clock Zero Cross ENSYNCn Enable Two-Pole Resonant Oscillator Load Register Load Logic OSCnFREQ REL* OSnTIS OSCnAMP OSnTIE OSnTAS OSCnPHAS OSnTAE Figure 35. Tone Generator Diagram Rev. 1.0 Si3220/Si3225 circuit with a programmable = cos(2 π f coeff /8000 Hz OSCnFREQ = coeff Desired Vrms -- - 1 coeff – 15 × ...

Page 60

... Si3220/Si3225 2 π 852   ---------------- - coeff = cos =   1 8000 OSC1FREQ = 0.78434 0.21556 15 × ( OSC1AMP = -------------------- - 2 – 1.78434 = 0x590 OSC1PHAS = 0 = cos (2 π 1336 / 8000) = 0.49819 coeff 2 14 OSC2FREQ = 0.49819 ( 8162 = 0x1FE2 0.50181 15 × ( OSC2AMP = -------------------- - 2 – 1.49819 = 0x942 OSC2PHAS = 0 The preceding computed values are written to the corresponding registers to initialize the oscillators ...

Page 61

... O2TALO/O2TAHI OSC2TA[15:0] O2TILO/O2TIHI OSC2TI[15:0] OMODE, OCON ZEROEN2, ROUT2, ENSYNC2, OSC2TAEN, OSC2TIEN, OSC2EN OS2TAS, OS2TIS, OS2TAE, OS2TIE Rev. 1.0 Si3220/Si3225 Description/Range (LSB Size) Sets oscillator frequency Sets oscillator amplitude Sets initial phase = (default 8.19 s (125 µ 8.19 s (125 µ s) Enables all Oscillator 1 param- ...

Page 62

... Si3220/Si3225 OSC1EN ... ... 0,1 , OSC1TA ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Message Parameter 1 Type Length Message Header Parameter Type Figure 37. On-Hook Caller ID Transmission Sequence 62 ... ... 0,1 , OSC1TI 0,1 Channel Mark Seizure Packet Parameter 2 Message Body ...

Page 63

... O1TALO/O1TAHI OSC1TA[15:0] FSKDAT FSKDAT[7:0] FSKFREQ0 FSKFREQ0[15:3] FSKFREQ1 FSKFREQ1[15:3] FSKAMP0 FSKAMP0[15:3] FSKAMP1 FSKAMP1[15:3] FSK01HI FSK01HI[15:3] FSK01LO FSK01LO[15:3] FSK10HI FSK10HI[15:3] FSK10LO FSK10LO[15:3] Rev. 1.0 Si3220/Si3225 O1FSK8 register bit. When Description/Range (LSB Size) Enable/disable 0 to 2.73 s (41.66 µ s)* Caller ID data Audio range Audio range 63 ...

Page 64

... Si3220/Si3225 Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "Tone Generator Architecture" on page 59 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz ...

Page 65

... Figure 38. Pulse Metering Generation Block Diagram DTMF Detection On-chip DTMF detection, also known as touch tone, is available in the Si3220 and Si3225 in-band signaling system that replaces the pulse- dial signaling standard. In DTMF, two tones generate a DTMF digit. One tone is chosen from the four possible row tones, and one tone is chosen from the four possible column tones ...

Page 66

... Si3220/Si3225 Table 39 outlines the hex codes corresponding to the detected DTMF digits. Table 39. DTMF Hex Codes Digit Hex code 0x1 1 0x2 2 0x3 3 0x4 4 0x5 5 0x6 6 0x7 7 0x8 8 0x9 9 0xA 0 0xB * 0xC # 0xD A 0xE B 0xF C 0x0 D Modem Tone Detection The Dual ProSLIC devices are capable of detecting a ...

Page 67

... RESET pin is pulled high and takes approximately achieve lock after RESET is released with stable PCLK and FSYNC. However, the settling time depends on the PCLK frequency and can be predicted based on the following equation: Rev. 1.0 Si3220/Si3225 , BUF paths, although implemented 1.544 MHz, 2 ...

Page 68

... Si3220/Si3225 64 -------------- - T = settle f PCLK PCLK PFD RESET Figure 40. PLL Frequency Synthesizer Interrupt Logic The Dual ProSLIC devices are capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Ground Key detected Power alarm DTMF digit detected Active timer 1 expired ...

Page 69

... The control byte has the following structure and is presented on the SDI pin MSB first CID[0] CID[1] Table 40. SPI Control Interface Rev. 1.0 Si3220/Si3225 CID[2] CID[3] 69 ...

Page 70

... Si3220/Si3225 SDO CS CPU SDI SPI Clock 70 Channel 0 CS SDO Channel 1 SCLK Channel 2 CS SDO Channel 3 SCLK Channel 14 CS SDO Channel 15 SCLK Figure 41. SPI Daisy-Chain Mode Rev. 1.0 SDI0 SDI SDI1 Dual ProSLIC #1 SDITHRU SDI2 SDI SDI3 Dual ProSLIC #2 SDITHRU SDI4 SDI14 ...

Page 71

... edge of SCLK after the DATA byte to indicate to the state machine that one byte The state of SDI is a “don’t care” during the DATA byte of a read operation. ADDRESS Rev. 1.0 Si3220/Si3225 CID[1] CID[2] CID[ should be transferred. only DATA [7:0] Hi-Z ...

Page 72

... Si3220/Si3225 CS SCLK SDI CONTROL SDO Figure 44. Register Read Operation via an 8-Bit SPI Port Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data indicates to the SPI state machine that eight more SCLK pulses follow to complete the operation ...

Page 73

... By keeping the address, data buffers, and RAMSTAT register on a per- channel basis, RAM address accesses can be scheduled for both channels without interface. ADDRESS DATA [15:8] ADDRESS DATA [15:8] ADDRESS Data [15:8] Rev. 1.0 Si3220/Si3225 DATA [7:0] Hi DATA [7:0] Data [7: ...

Page 74

... Si3220/Si3225 CS SCLK SDI CONTROL SDO Figure 50. RAM Read Operation via a 16-Bit SPI Port PCM Interface The Dual ProSLIC devices programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the PCLK and FSYNC inputs, PCM Mode Select, ...

Page 75

... DSP. The data format is 2s complement with MSB first (sign bit). Transmitting and receiving data via Linear mode requires two continuous time slots. An 8-bit Linear mode enables 8-bit transmission without companding MSB MSB Rev. 1.0 Si3220/Si3225 HI LSB ...

Page 76

... Si3220/Si3225 PCLK FSYNC PCLK_CNT 0 1 DRX MSB DTX HI-Z MSB Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC Rev. 1 LSB HI-Z LSB ...

Page 77

... Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. Value at Segment Endpoints Digital Code 8159 10000000b . . . 4319 4063 10001111b . . . 2143 2015 10011111b . . . 1055 991 10101111b . . . 511 479 10111111b . . . 239 223 11001111b . . . 103 95 11011111b . . . 35 31 11101111b . . . 3 1 11111110b 0 11111111b Rev. 1.0 Si3220/Si3225 * Decode Level 8031 4191 2079 1023 495 231 ...

Page 78

... Si3220/Si3225 Table 42. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of even-numbered bits. Other available formats include inversion of odd bits, inversion of all bits bit inversion. See "PCM Companding" on page 75 for more details. ...

Page 79

... GCI Data Transmit initialization and setup of the device, and one Signaling GCI Data Receive and Control channel, SC, used for communicating the status of the device and initiating commands. Within the SC channel are six Command/Indicate (C/I) bits and two Rev. 1.0 Si3220/Si3225 SDI SDO ...

Page 80

... Si3220/Si3225 handshaking bits, MR and MX. The C/I bits indicate status and command communication handshaking bits Monitor Receive, MR, and Monitor Transmit, MX, exchange data in the Monitor channel. Figure 55 illustrates the contents of a GCI highway frame. 16-Bit GCI Mode In addition to the standard 8-bit GCI mode, the Dual ...

Page 81

... Monitor channel is less than 8 kbps. 125 µ Frame CH1 CH2 C 2nd Byte 3rd Byte ACK ACK 1st Byte 2nd Byte 125 µ s Rev. 1.0 Si3220/Si3225 CH3 Unused ACK 3rd Byte 81 ...

Page 82

... Si3220/Si3225 The Idle state is achieved by the MX and MR bits being held inactive for two or more frames. When a transmission is initiated by a host device, an active state is seen on the downstream MX bit. This signals the Dual ProSLIC that a transmission has begun on the Monitor channel and it should begin accepting data from it. After ...

Page 83

... bit calcu lated and tran s m itted on d ata ups tream (D TX) line. MX received d ata dow n s trea lin e. LL: Las t look of m onitor b yte received line. ABT: Abort ind ication to in terna l s ource. Figure 58. Dual ProSLIC Monitor Receiver State Diagram Si3220/Si3225 Initial S tate bort ...

Page 84

... Si3220/Si3225 Idle RQT RQT RQT nth RQT Wait RQT bit received line. MX: MX bit calculated and expected line. MXR : MX bit s am pled line. C LS: C ollis ion w ithin the m onitor data byte line. R QT: R eques t for trans ion from internal s ource. ABT: Abort reques t/indication. ...

Page 85

... Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver for correct communication with the Dual Si3220/Si3225 ProSLIC. Devices that do not accept this “best case” timing scenario will communicate with the Dual ProSLIC ...

Page 86

... Si3220/Si3225 Monitor Data Downstream $01 $FF $FF $91 $91 125 µs 1 Frame MX Downstream Bit MR Downstream Bit Monitor Data Upstream $FF $FF $FF $FF $FF MX Upstream Bit MR Upstream Bit = Acknowledgement of data reception Figure 61. Example Write to Registers $10 and $11 in Channel 0 of the Dual ProSLIC 86 $01 $10 $10 Data to be ...

Page 87

... Dual ProSLIC digital I/O port when used in GCI mode. The SC channel consists of six C/I bits and two 0 handshaking bits as described in the tables below. The functionality of the handshaking bits is defined in the Rev. 1.0 Si3220/Si3225 MSB LSB ...

Page 88

... Si3220/Si3225 monitor channel section. This section defines the functionality of the six C/I bits whether they are being transmitted to the GCI bus via the DTX pin (upstream) or received from the GCI bus via the DRX pin (downstream). The structure of the SC channel is shown in Figure 62. ...

Page 89

... SC channel byte to the OPEN state for two consecutive cycles and then resetting the downstream SC channel byte to the intended linefeed state for two consecutive Rev. 1.0 Si3220/Si3225 thresholds and control the linefeed ...

Page 90

... Si3220/Si3225 cycles. If the Dual ProSLIC continues to automatically transition to the OPEN state, the power alarm threshold might be set incorrectly. If this problem persists after the power alarm settings are verified, a system fault is probable, and the user should take measures to diagnose the problem. Upstream (Transmit) SC Channel Byte ...

Page 91

... The user can bypass the companding process and interface directly to the 16-bit data. Si3220/Si3225 A third digital loopback takes the digital stream at the output of the µ-Law/A-Law expander and feeds it back to the input of the µ-Law/A-Law compressor. ...

Page 92

... REN without causing the terminal equipment to ring audibly. This ringing signal can be either balance or unbalanced depending on the state of the RINGUNB bit of the RINGCON register. This feature is also available with the Si3225 provided that a sufficient battery voltage is present. Rev. 1.0 Comments ±5% ± ...

Page 93

... I = ringing current when using an external RING,EXT ringing source (Si3225 only) The SLIC diagnostic capability consists of a peak detect block and two filter blocks, one for dc and one for ac. The topology is illustrated in Figure 64. The peak detect filter block reports the magnitude of the largest positive or negative value without sign ...

Page 94

... Si3220/Si3225 Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on and off times of the ringing and pulse-metering signals. The tone generation oscillator can be used to program a time period for averaging specific measured test parameters. Transmit audio path diagnostics filter. Transmit ...

Page 95

... Intermodulation distortion measurement (two- tone method). Measures the intermodulation distortion product in the presence of two tones. It can be implemented by programming the three IIR diagnostic filter stages to provide two notches at the two tone frequencies and a peak at the frequency of interest. Si3220/Si3225 Rev. 1.0 95 ...

Page 96

... Capacitor used in low-pass filter to stabilize SLIC feedback loops. Component Reference Ground. Return path for differential and common-mode capacitors. Do not connect to system ground. Rev. 1 RRDa SDITHRU 45 SDI 44 SDO 43 SCLK Si3225 42 VDD4 41 GND4 64-Lead TQFP 40 INT (epad) 39 PCLK 38 GND3 37 VDD3 36 DTX 35 DRX 34 FSYNC 33 RESET ...

Page 97

... Also modulates ac current onto RING side of loop. I Temperature Sensor. Senses Internal temperature of Si3200. Connect to THERM pin of Si3200 when using discrete linefeed circuit Test Relay Driver Output. Drives test relays for connecting loop test equipment. Rev. 1.0 Si3220/Si3225 BAT BAT 97 ...

Page 98

... Si3220/Si3225 Symbol Pin Number(s) Si3220 Si3225 28, 52 28, 52 RTRPb, RTRPa 30, 50 30, 50 TRD2b, TRD2a 31, 48 RRDb, RRDa 31, 48 GPOb, GPOa 32, 49 32, 49 BATSELb, BATSELa 35 35 DRX 36 36 DTX 39 39 PCLK 33 33 RESET 34 34 FSYNC 40 40 INT 43 43 SCLK 44 44 SDO 45 45 ...

Page 99

... Senses ring-trip condition when using centralized ring genera- tor. Connect to high side of ring sense resistor. Shared by channels a and b. Exposed Die Paddle Ground. Connect to a low-impedance ground plane via top side PCB pad directly under the part. See Package Outlines: 64-Pin TQFP for PCB pad dimensions. Rev. 1.0 Si3220/Si3225 99 ...

Page 100

... Main power supply for all internal circuitry. Connect supply. Decouple locally with a 0.1 µF/10 V capacitor. Battery Voltage Select. Connect to the BATSEL pin of the Si3220 or Si3225 through an external resistor to enable automatic battery switching. No connection is required when used with the Si3225 in a single battery system configuration. ...

Page 101

... THERM O Thermal Sensor. Connect to THERM pin of Si3220 or Si3225. 15 ITIPN I Negative TIP Current Control. Connect to the ITIPN lead of the Si3220 or Si3225. 16 ITIPP I Positive TIP Current Control. Connect to the ITIPP lead of the Si3220 or Si3225. epad GND Exposed Die Paddle Ground. For adequate thermal management, the exposed die paddle should be sol- dered to a PCB pad that is connected to low-impedance inner and/or back- side ground planes using multiple vias. See “ ...

Page 102

... Si3220/Si3225 Package Outline: 64-Pin TQFP Figure 65 illustrates the package details for the Dual ProSLIC. Table 51 lists the values for the dimensions shown in the illustration See Detail A See Detail B Figure 65. 64-Pin Thin Quad Flat Package (TQFP) Table 51. 64-Pin Package Diagram Dimensions 102 ...

Page 103

... A1 0.03 0.13 B .33 .51 C .19 .25 D 9.80 10.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h .25 .50 L .40 1.27 γ — 0.10 θ 0º 8º *Note: Typical parameters are for information purposes only. Rev. 1.0 Si3220/Si3225 h 0.010 GAUGE PLANE C See Detail F 103 ...

Page 104

... Si3220/Si3225 System Demonstration Kit User's Guide“ “AN74: SiLINKPS-EVB User's Guide“ “AN75: Dual ProSLIC Software interface“ “AN86: Ringing / Ringtrip Operation and Architecture on the Si3220/Si3225“ “AN88: Dual ProSLIC Line Card Design“ “AN91: Si3200 Power Offload Circuit“ ...

Page 105

... Broadcom VoB ICs with integrated codecs. Globally-programmable FXO port 5000 V isolation. Data rates from 300 bps kbps; supports V.90, V.34, V.32 BIS, and others 16-Bits dynamic range; direct DSP interface; 3:1 analog input mixer. Rev. 1.0 Si3220/Si3225 Comments 105 ...

Page 106

... Eliminated register summary table. Refer to “AN58: Si3220/Si3225 Programmer’s Guide”. “16-Bit RAM Address Summary”, on page 94 Eliminated RAM address summary table. Refer to “AN58: Si3220/Si3225 Programmer’s Guide”. "Package Outline: 16-Pin ESOIC" on page 103 Changed A1 specification to .076 REF. Revision 0.95 to Revision 0.96 Table 1, “ ...

Page 107

... Added resistors R23, R24, R25, R26, R27 and R28. Table 15, “Si3220 + Si3200 External Component Values,” on page 27 Added resistors R20–R25. Si3220/Si3225 Table 16, “Si3225 + Si3200 External Component Values,” on page 27 Added resistors R23–R28. "Adaptive Linefeed" on page 32 Improved text describing loop start and ground start operation ...

Page 108

... Si3220/Si3225 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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