SI3225-G-GQ Silicon Laboratories Inc, SI3225-G-GQ Datasheet - Page 56

IC PROSLIC/CODEC DUAL 64TQFP

SI3225-G-GQ

Manufacturer Part Number
SI3225-G-GQ
Description
IC PROSLIC/CODEC DUAL 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet

Specifications of SI3225-G-GQ

Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
65mA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3225-G-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI3225-G-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Si3220/25 Si3200/02
3.15.3. Loop Closure Mask
The Dual ProSLIC implements a loop closure mask to
ensure mode change between ringing and active or on-
hook transmission without causing an erroneous loop
closure detection. The loop closure mask register,
LCRMASK, should be set such that loop closure
detection is ignored for the time (LCRMASK 1.25 ms/
LSB). The programmed time is set to mask detection of
transitional currents that occur when exiting the ringing
mode while driving a reactive load (i.e., 5 REN). A
typical setting is 80 ms (LCRMASK = 0x40).
56
Notes:
Ringing
(Si3220)
(Si3225)
External
Method
Parameter
Ring Trip Interrupt Pending
Ring Trip Interrupt Enable
AC Ring Trip Threshold
DC Ring Trip Threshold
Ring Trip Sample Period
Linefeed Shadow (monitor only)
Ring Trip Detect Status
(monitor only)
AC Ring Trip Detect Debounce
Interval
DC Ring Trip Detect Debounce
Interval
Loop Current Sense
(monitor only)
Internal
1. All calculated values should be rounded to the nearest integer.
2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations.
Table 30. Recommended Values for Ring Trip Registers and RAM Addresses
Frequency
16–32 Hz
33–60 Hz
16–32 Hz
33–60 Hz
Ringing
Table 31. Register and RAM Locations Used for Ring Trip Detection
Added?
Offset
Yes
Yes
Yes
Yes
DC
No
No
Register/RAM
800/f
800/f
800/f
RTPER
2(800/
2(800/
2(800/
Mnemonic
f
f
f
LINEFEED
RING
RING
RING
IRQVEC2
RTDCDB
RTDCTA
LCRRTP
RTACDB
RTACTH
IRQEN2
RTPER
ILOOP
RING
RING
RING
)
)
)
1.59 x V
1.59 x V
Rev. 1.3
221 x RTPER
221 x RTPER
RTDCTH[15:0]
RTDCDB[15:0]
Register/RAM
RTACDB[15:0]
RTACTH[15:0]
RTPER[15:0]
ILOOP[15:0]
RTACTH
RING,PK
RING,PK
3.15.4. Si3220 Ring Trip Detection
The Si3220 provides the ability to process a ring trip
event using an ac-based detection scheme. Using this
scheme eliminates the need to add dc offset to the
ringing signal, which reduces the total power dissipation
during the ringing state and maximizes the available
ringing amplitude. This scheme is valid for shorter loop
lengths only since it cannot reliably detect a ring trip
event if the off-hook line impedance overlaps the on-
hook impedance at 20 Hz.
32767
32767
LFS[2:0]
RTRIPS
RTRIPE
RTP
Bits
x RTPER
x RTPER
0.067 x RTPER x V
0.067 x RTPER x V
Enabled/Disabled
0.577(RTPER x V
0.577(RTPER x V
Programmable
0 to 101.09 mA
See Table 30
See Table 30
See Table 30
0 to 40.96 s
0 to 40.96 s
Yes/No
Range
RTDCTH
N/A
N/A
32767
32767
OFF
OFF
OFF
OFF
)
)
Resolution
1
Table 21
1.25 ms
1.25 ms
See Note 2
RTACDB/
RTDCDB
See
N/A
N/A
N/A
N/A

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