SI3225-G-GQ Silicon Laboratories Inc, SI3225-G-GQ Datasheet - Page 93

IC PROSLIC/CODEC DUAL 64TQFP

SI3225-G-GQ

Manufacturer Part Number
SI3225-G-GQ
Description
IC PROSLIC/CODEC DUAL 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet

Specifications of SI3225-G-GQ

Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
65mA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3225-G-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI3225-G-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
monitor channel section. This section defines the
functionality of the six C/I bits whether they are being
transmitted to the GCI bus via the DTX pin (upstream)
or received from the GCI bus via the DRX pin
(downstream). The structure of the SC channel is
shown in Figure 62.
3.31.9. Downstream (Receive) SC Channel Byte
The first six bits in the downstream SC channel control
both channels of the Dual ProSLIC where the C/I bits
are defined as follows:
Table 49. Programming Operating Modes Using
CI2A, CI1A, CI0A Used to select operating mode for
CI2B, CI1B, CI0B Used to select operating mode for
MR, MX
MSB
CI2A
Channel Specific C/I bits
Note: x = A or B, corresponding to Channel A or
CI2x
7
0
0
0
0
1
1
1
1
Channel B.
CI1A
Downstream SC Channel C/I Bits
Figure 62. SC Channel Structure
6
CI1x
0
0
1
1
0
0
1
1
CI0A
5
channel A
channel B
Monitor channel handshake bits
CI0x
0
1
0
1
0
1
0
1
CI2B
4
Dual ProSLIC Operating
Mode
Open (high impedence,
no line monitoring)
Forward Active
Forward On-Hook Trans-
mission
Ground Start (Tip Open)
Ringing
Reverse Active
Reverse On-Hook Trans-
mission
Ground Start (Ring
Open)
CI1B
3
CI0B
2
MR
1
LSB
MX
0
Rev. 1.3
Figure 63 illustrates the transmission protocol for the C/I
bits within the downstream SC channel. New data
received by either channel must be present and match
for two consecutive frames to be considered valid.
When a new command is communicated via the
downstream C/I bits, this data must be sent for at least
two consecutive frames to be recognized by the Dual
ProSLIC.
The current state of the C/I bits is stored in a primary
register, P. If the received C/I bits are identical to the
current state, no action is taken. If the received C/I bits
differ from those in register P, the new set of C/I bits is
loaded into secondary register S, and a latch is set.
When the next set of C/I bits is received during the
frame that immediately follows, the following rules
apply:
If the received C/I bits are identical to the contents of
register S, the stored C/I bits are loaded into register
P, and a valid C/I bit transition is recognized. The
latch is reset, and the Dual ProSLIC responds
accordingly to the command represented by the new
C/I bits.
If the received C/I bits differ from both the contents of
register S and the contents of register P, the newly-
received C/I bits are loaded into register S, and the
latch remains set. This cycle continues as long as
any new set of C/I bits differs from the contents of
registers S and P.
If the newly-received C/I bits are identical to the
contents of register P, the contents of register P
remain unchanged, and the latch is reset.
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93

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