PEB2245N-V12 Infineon Technologies, PEB2245N-V12 Datasheet
PEB2245N-V12
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PEB2245N-V12IN
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PEB2245N-V12 Summary of contents
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ICs for Communications Multipoint Switching and Conferencing Unit - Attenuation MUSAC PEB 2245 Version 1.2 Data Sheet 03.96 T2245-XV12-D1-7600 ...
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PEB 2245 Revision History: Previous Version: Page (in Page (in Subjects (major changes since last revision) Version current 01.94) Version) 163 8 Version 1.2 189 34 Figure 18 (Initializing the PEB 2245 for a 4096-kHz Device Clock) corrected 201 46 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 8 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview A Complete Family of Efficient Solutions If the issue is digital switching and conferencing, the solution is flexibility, capacity, and economy. Siemens Semiconductor offers the most economical answer to all conceivable applications in this field. Our complete family ...
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The figure below shows the general architecture of a digital exchange. Figure 1 General Exchange Architecture System Background Digital exchanges put calls through by newly arranging the speech signals coded with 8-bit words (PCM time-slots). The code words are transmitted ...
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An overview on the complete switching and conferencing IC-family is shown in the following table: Table 1 Complete Switching and Conferencing IC Family MTSC MTSS PEB 2045 PEB 2046 Switching 512 256 256 256 capacity (time-slots) Input/output ‘16/8 ‘8/8 lines ...
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Multipoint Switching and Conferencing Unit TM (MUSAC ) Preliminary Data 1.1 Features Switching Time/space switch for 2048-, 4096- or 8192-kbit/s PCM systems Switching 512 incoming PCM-channels 256 outgoing PCM channels 16 input and 8 ...
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Conference Mode conference channels in any combination independent conferences simultaneously (3 subscribers) Programmable attenuation (0/3/6/9 dB) on each input channel Programmable attenuation (0/3 dB) on each output channel Programmable PCM-level adaption (attenuation or amplification) ...
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Pin Definitions and Functions Pin No. Symbol Input (I) Output ( INT IN1 I 7 IN5 I 9 IN9 I 11 IN13 I 13 IN14 I 14 IN15 I ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output ( R ALE I 26 AD0 I/O 27 AD1 I/O 29 AD2 I/O 30 AD3 I/O 31 AD4 I/O ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 39 RES I 44 CLK I Semiconductor Group Function Reset: A high signal on this input forces the MUSAC into reset state. The minimum pulse length is four ...
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Functional Symbols Figure 3 Functional Symbol for the Standard Configuration Figure 4 Functional Symbol for the Primary Access Configuration Semiconductor Group 13 PEB 2245 ...
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Device Overview The Multipoint Switching and Conferencing Unit (MUSAC) combines a time switch unit (MTSC) and a powerful signal processor on one chip. The MUSAC enhances the capabilities of a PBX by supporting teleconferencing and multipoint data communication over ...
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System Integration Conferencing The MUSAC is designed to connect any of the 512 PCM-input channels to any of 256 output channels. Any input channel total number of 64 can be handled in 21 independent conferences simultaneously. ...
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Figure 7 shows the architecture of a primary access board with common channel signaling using four CMOS devices. Figure 7 Architecture of a Primary Access Board Multipoint Switching In a multipoint configuration the communication between different stations is done by ...
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Figure 8 Multipoint System Configuration for ISDN Subscribers Semiconductor Group 17 PEB 2245 ...
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In order to establish a multipoint-connection with more than 64 terminals, you can form a multistage arrangement, as shown in figure 9. Figure 9 Multistage Arrangement Semiconductor Group 18 PEB 2245 ...
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Functional Description Figure 10 Detailed Block Diagram of the PEB 2245 2.1 Basic Functional Principles The MUSAC is a memory time switch device for a PCM PBX system, offering a variety of additional features like multipoint switching, conference calls, ...
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The block diagram is shown in figure 10. The MUSAC is designed to connect any of 512 PCM-input channels to any of 256 output channels. Any input channel total number of 64 can be handled in 21 ...
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A tone to be inserted into a conference is handled as an additional conference subscriber using any input PCM channel (access to CCM) but without assigning an output time-slot (no access to CM). Multipoint switching is a special form of ...
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Table 2 Possible Input Modes Input Modes 16 2048 8 4096 4 8192 2 8192 + 8 2048 4 4096 + 8 2048 The PEB 2245 runs with either a 4096 8192-kHz device clock as selected with CFR:CPS. ...
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Figure 11 Latching Instant for Input Data Semiconductor Group 23 PEB 2245 ...
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The four most significant bits of the clock shift register are of interest for the input lines. They only affect the odd input lines (see section Clock Shift Register): The frame structure can be advanced by the number of bit ...
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Assuming a CSR entry X0 Programming the XS2, XS1 and XS0 bits with a value deviating from binary 000 the output frame is delayed by 8 -(XS2, XS1, XS0) D frame by 7-bit periods relative to the rising SP-pulse edge. ...
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Time Slot 127 - 6 7 Time Slot Time Slot Time Slot 127 - 6 7 Time Slot Time Slot 31 6 ...
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Configuration Type The MUSAC works either in the standard configuration for usual switching applications or in the primary access configuration. In these both configurations the conference and multipoint switching capability can be used. Standard Configuration A logical 1 in the ...
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Figure 13 SYP Duration for Primary Access Configuration A logical 0 in the CFS bit of the configuration register selects the PEB 2245 for primary access applications. In this case the MUSAC is an interface device connecting ...
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Figure 14 Connection Choices in the Primary Access Configuration 2.2 Microprocessor Interface and Registers The MUSAC is programmed via the P interface. It consists of the address data bus AD7 … AD0, the address bits A1 … A0, the Write ...
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Table 4 P-Interface Functions ALE Type of P-Interface Fixed to V Motorola DD Fixed to ground Intel Switching Intel In the multiplexed P-interface mode A0, A1 have to be fixed to logical 0. For a demultiplexed P interface the address ...
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Indirect access to the CFR, CSR CCM: An indirect access is performed by reading/writing three consecutive bytes (first byte = control byte, second byte = data byte, third byte = address byte) to/from IAR. Bit ...
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Figure 16 Timing Diagrams of IAR Semiconductor Group 32 PEB 2245 ...
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Operational Description 3.1 Reset State After a hardware reset (RES) the MUSAC is set to its initial state. The MOD- and CFR-register bits are all set to logical 1; the CSR, CST and CMR register bits are set to ...
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Figure 18 Initializing the PEB 2245 for a 4096-kHz Device Clock 3.3 Operation with a 4096-kHz Device Clock In order for the MUSAC to operate with a 4096-kHz device clock the CPS bit in the CFR register needs to be ...
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Detailed Register Description The following registers may be accessed: Table 6 Addressing the Direct Registers Address Demultiplexed Multiplexed Mode A (1:0) Mode AD (7: ...
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Table 7 Input/Output Operating Modes MI1 MI0 MO1 ...
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Table 8 Input and Output Pin Arrangement for the Standard Configuration Input Pin Arrangement Pin No Mbit Mbit/s 4 IN1 5 IN0 7 IN5 8 IN4 9 IN9 10 IN8 11 IN13 IN12 12 IN14 13 ...
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Table 9 Input, Output and Tristate Pin Arrangement for the Primary Access Configuration Pin No. Pin Name P-LCC 2 MHz TSC0 5 TSC0 TSC1 8 TSC1 TSC2 10 TSC2 TSC3 12 TSC3 OUT0 43 OUT0 OUT2 41 OUT1 OUT4 38 ...
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Status Register (STA) Access in the multiplexed P-interface mode: Access in the demultiplexed P-interface mode: AD7 don’t care B Busy: The chip is busy resetting the connection memory ( undefined after power ...
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Conference Mask Register (CMR) Access in the multiplexed P-interface mode: Access in the demultiplexed P-interface mode: Reset value AD7 logical 1 disables the corresponding interrupt. IR Initialization Request mask; the initialization request is masked ...
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Access to CM DIO = 0 Transparent Switching (i.e. the MUSAC works exactly like a MTSC) D9 Validity bit: A logical 0 enables the programmed connection, a logical 1 tristates the outputs D8 … D0 Logical line and time-slot number ...
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Table 11 Time-Slot and Line Programming for the Primary Access Configuration 2-Mbit/s input lines 4-Mbit/s input lines 8-Mbit/s input lines 2-Mbit/s output lines 4-Mbit/s output lines 8-Mbit/s output lines The interface select bits have to be programmed as shown in ...
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Access 2 to CCM DI0 Logical 0 D9/D8 Noise suppression threshold D7/D6 Input attenuation level D5 Output attenuation level Note: D7, D6, D5 are only relevant to conference mode; in the multipoint switching mode these bits must be logical 0. ...
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Indirect Registers Configuration Register (CFR) Access: Read or write at address FE Reset value AD7 1 1 CPS Clock Period Select: Device clock is set to 8192 kHz (logical 1) or 4096 kHz (logical 0). CFS Configuration ...
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RRE Receive with Rising Edge. The data is sampled with the falling (RRE = 0) or rising edge (RRE = 1) of the data equivalent clock. XS0 … XS2 Transmit clock Shift, bits 2 – 0. The transmitted data stream ...
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Electrical Characteristics 5.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on any pin with respect to ground Maximum voltage on any pin Note: Stresses above those listed here may cause permanent damage to the device. ...
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AC Characteristics Ambient temperature under bias range, Inputs are driven at 2.4 V for a logical 1 and at 0.4 V for a logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 ...
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Figure 21 Microprocessor Interface Timing Intel Bus Mode Semiconductor Group 48 PEB 2245 ...
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Microprocessor Interface Timing 5.5.1 Motorola Bus Mode Figure 22 P Write Cycle Figure 23 Multiplexed Address Timing Figure 24 Non-multiplexed Address Timing Semiconductor Group 49 PEB 2245 ...
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Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time to WR, RD Address hold time from WR, RD ALE pulse delay DS delay after R/W ...
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Clock and Synchronization Timing Parameter Clock period 8 MHz high Clock period 8 MHz low Clock period 8 MHz Synchronization pulse setup 8 MHz Synchronization pulse delay 8 MHz Clock period 4 MHz high Clock period 4 MHz low Clock ...
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CLK Mbit/s OUT 2 Mbit Mbit OUT 4 Mbit/s TS 127 IN 8 Mbit/s Bit 4 TS OUT 8 Mbit/s Bit Example with delayed output frame SP N ...
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CLK Mbit Mbit Mbit 127 Bit 4 8 Mbit/s OUT 2 Mbit/s OUT 2 Mbit/s OUT TS 4 Mbit/s OUT TS 127 Bit 4 8 Mbit/s TSC 2 Mbit/s TSC ...
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Figure 27 PCM-Line Timing in Standard Configuration with a 4-MHz Device Clock Semiconductor Group 54 PEB 2245 ...
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Figure 28 PCM-Line Timing in Primary Access Configuration with a 4-MHz Device Clock and a CSR Entry (00010001) Semiconductor Group 55 PEB 2245 ...
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Table 13 Busy Times Operation Indirect register access Connection memory reset Semiconductor Group Max. Value 900 250 56 PEB 2245 Unit ns s ...
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Conference Applications of the MUSAC Figure 29 Data Flow through the MUSAC Semiconductor Group Case of Conferencing 57 PEB 2245 ...
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The PCM samples of each input channel first pass through an input processing stage. In this stage, an input attenuation level ( dB) and a noise suppression threshold can be programmed individually for each channel. Following ...
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Procedure for Programming a Conference Configuration Register CFR The conference mode must be selected by setting CFR: The PCM encoding law must be selected, A-law (CFR:CUA0 = 1) or -law (CFR:CUA0 = 0). The PCM-byte format must be ...
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Application Hints Connection and disconnection of individual participants from a conference: Subscribers can be connected and disconnected “on the fly” from a conference. A subscriber is disconnected from a conference by writing an invalid conference number (e. ...
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Meaning of Bits when Writing to the CCM and CM in Conference Mode A write access to indirect registers and to the CM and CCM is performed by writing a 3-byte sequence to the IAR register: 1st writing: IAR = ...
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CONF Conference mode (1) or transparent mode (0) VAL Validity, output is enabled (0) or disabled (1) OTS4 … 0 Output Time-Slot number (0 – 31) OL2 … 0 Output Line number (0 – 7) Example of Programming a 4-Party ...
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CCM Input Channel 3: W: IAR = 0110 0000 W: CCM 1st access W: IAR = 1001 0100 in I4, ts9 W: IAR = 0000 0001 cca = 01 W: IAR = 1010 0000 W: CCM 2nd access W: IAR ...
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Reading Back the CCM and the CM Contents of Subscriber 2: CCM Input Channel 2: W: IAR = 0100 0000 R: CCM 1st access (K2 – 010) W: IAR = 0000 0000 data don’t care e. ...
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Package Outlines P-LCC-44 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 65 PEB 2245 Dimensions in mm ...
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Appendix 8.1 Initialization for Conferencing in a PBX 1) See table 7. 2) See table 8. Figure 30 Semiconductor Group 66 PEB 2245 ...
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Programming a Conference in a PBX Figure 31 Table 14 Procedure for each Conference 1. Make a list of the conference subscribers 2. Determine the input time slot Determine the logical input port 3. Determine the output time slot ...
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Programming Procedure for Switching TS’s – Select a column for input and output rate – Fill in the values of the bits – Write the 3 bytes (from top to bottom) to register IAR 2 MBit/s Output Rate 3 ...
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Programming Procedure for a PBX Conference – Select a column for input and output rate – Fill in the values of the bits by aid of chapter 8.1 and 8.2 – Write the 9 bytes (from top to bottom) ...
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INV PCM data inverted (= 1) or not (= 0) ITS6 0 Input time slot number IL0 3 Logical input line number CCA5 0 Conference control address NOI1 0 Noise suppression threshold noise suppression ...