SLXT973QC Cortina Systems Inc, SLXT973QC Datasheet - Page 28

• Manufacturer Part Number: SLXT973QC
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QC

• Lead Free Status / Rohs Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
3.3.8.1
Figure 5
Figure 6
Cortina Systems
MII Management Interface
The LXT973 Transceiver supports the IEEE 802.3 MII Management Interface also known
as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer
devices to monitor and control the state of the LXT973 Transceiver. The MDIO interface
consists of a physical connection, a specific protocol which runs across the connection,
and an internal set of addressable registers. The physical interface consists of a data line
(MDIO) and clock line (MDC), and a control line (MDDIS). The maximum speed of MDC is
20 MHz.
Operation of this interface is controlled by the MDDISn input pin. When MDDISn is High,
the MDIO is completely disabled. When MDDISn is Low, read and write are enabled. The
timing for the MDIO Interface is shown in
operations, and
communicate with multiple
LXT973 Transceiver devices. Each LXT973 Transceiver port is assigned an address
between 0 and 31, as described in
The LXT973 Transceiver supports the core 16-bit MDIO registers. Registers 0-10 and 15
are required and their functions are specified by the IEEE 802.3 specification. Additional
registers are included for expanded functionality. Specific bits in the registers are
referenced using an “X.Y” notation, where X is the register number (0-31) and Y is the bit
number (0-15)
Management Interface Read Frame Structure
Management Interface Write Frame Structure
®
MDIO
(Read)
MDC
(Write)
MDIO
High Z
MDC
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Idle
Preamble
32 "1"s
Preamble
32 "1"s
0
0
ST
Figure 6
ST
1
1
1
0
Op Code
Op Code
for write operations. The protocol allows one controller to
0
1
Write
A4
A4
PHY Address
PHY Address
Table 5 on page 20
A3
A3
A0
A0
Table 49 on page
Write
R4
R4
Register Address
Register Address
R3
R3
R0
R0
(ADDR<4:1>).
Z
Around
Turn
1
Around
Turn
0
89. See
0
D15
D15
D15
D14
Figure 5
Data
Read
D14
D14
D1
Data
3.3 MII Operation
D1
D1
D0
for read
D0
Idle
Page 28
Idle