SLXT973QC Cortina Systems Inc, SLXT973QC Datasheet - Page 31

• Manufacturer Part Number: SLXT973QC
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QC

• Lead Free Status / Rohs Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
3.5.3
3.5.3.1
3.5.3.2
3.5.4
Cortina Systems
Power-Down Mode
The LXT973 Transceiver incorporates numerous features to maintain the lowest power
possible. The device can be put into a low-power state via Register 0 as well as a near-
zero power state with the power-down pins. When in power-down mode, the device is not
capable of receiving or transmitting packets.
The lowest power operation is achieved using the global power-down pins. These active
High pins power down every circuit in the device, including the clocks. All registers are
unaltered and maintained. When the power-down pins are released, the registers are
reloaded with the value of the last hardware reset.
Individual ports (software power-down) can be powered down using Control Register bit
0.11. This bit powers down a significant portion of the port, but clocks to the register
section remain active. This allows the management interface to remain active during
register power-down. The power-down bit is active High.
Hardware Power-Down
The hardware power-down per port mode is controlled by the PWRDWN 0/1 pins. When
PWRDWN 0/1 is High, the following conditions are true:
Software Power-Down
Software port power-down control is provided by Register bit 0.11 in the respective port
Control Registers (refer to
following conditions are true:
Reset
The LXT973 Transceiver provides both hardware and software resets. Configuration
control of auto-negotiation, speed, and duplex mode selection is handled differently for
each. During a hardware reset, settings for Register bits 0.13, 0.12, and 0.8 are read in
from the pins (refer to
register bit definitions).
During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the
pins, and revert back to the values that were read in during the last hardware reset. Any
changes to pin values from the last hardware reset are not detected during a software
reset. Also, during a software reset (Register bit 0.15 = 1), the registers are available for
reading. The reset bit is polled to see when the part has completed reset (Register bit 0.15
= 0).
During a hardware reset, register information is unavailable for 1 ms after de-assertion of
the reset. All the MII interface pins are disabled during a hardware reset and released to
the bus on de-assertion of reset.
®
• LXT973 Transceiver ports and the clock are shut down.
• Outputs are three-stated.
• The MDIO registers are not accessible.
• Configuration pins are not read upon release of the PWRDWN 0/1 pins, and registers
• The individual port is shut down.
• The MDIO registers remain accessible.
• The register remains unchanged.
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
are reloaded with the value of the last hardware reset.
Table 9 on page 32
Table 16 on page
for pin settings and
66). During individual port power-down, the
Table 16 on page 66
3.5 Initialization
Page 31
for