SLXT973QC Cortina Systems Inc, SLXT973QC Datasheet - Page 82

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SLXT973QC

Manufacturer Part Number
SLXT973QC
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of SLXT973QC

Lead Free Status / Rohs Status
Not Compliant

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LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Figure 30
Table 41
Cortina Systems
100BASE-TX Receive Timing - 4B Mode
MII - 100BASE-TX Receive Timing Parameters - 4B Mode
®
RXD<3:0>, RXDV, RXER setup
to RXCLK High
RXD<3:0>, RXDV, RXER hold
from RXCLK High
CRS asserted to RXD<3:0>,
RXDV
Receive start of
“J” to CRS asserted
Receive start of “T” to CRS de-
asserted
Receive start of “J” to COL
asserted
Receive start of “T” to COL de-
asserted
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
production testing.
Parameter
Note:
Twisted-Pair
RXD<3:0>
RXCLK
Twisted-pair input default pins are as follows: DPBP/N_0 and
DPAP/N_1.
RXDV
Input
CRS
COL
0ns
Sym
t1
t2
t3
t4
t5
t6
t7
t4
t6
Min
10
10
11
10
10
14
3
Typ
14
17
4
t3
1
250ns
Max
16
17
15
20
5
t5
t7
t1
t2
Units
BT
BT
BT
BT
BT
ns
ns
15.0 Timing Diagrams
Conditions
Test
Page 82

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