SLXT973QC Cortina Systems Inc, SLXT973QC Datasheet - Page 91

• Manufacturer Part Number: SLXT973QC
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QC

• Lead Free Status / Rohs Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Figure 42
Table 51
Cortina Systems
RESET Pulse Width and Recovery Timing
RESET Pulse Width and Recovery Timing Parameters
®
RESET pulse width
RESET recovery delay
1. Typical values are at 25
2. Reset recovery delay is specified as a maximum value because it refers to the PHY’s guaranteed
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
MDIO,etc.
testing.
performance. - the PHY comes out of reset after a delay of no more than 300 μ S. System designers
should consider this as a minimum value. After de-asserting RESET, the MAC should delay no less than
300 μ S before accessing the MDIO port.
RESET
Parameter
2
o
C and are for design aid only; not guaranteed and not subject to producing
Sym
t1
t2
Min
10
–
Typ
–
–
1
t
1
Max
300
–
Units
η s
μ s
15.0 Timing Diagrams
t
2
Conditions
Test
–
–
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