SC16IS762IBS,151 NXP Semiconductors, SC16IS762IBS,151 Datasheet
SC16IS762IBS,151
Specifications of SC16IS762IBS,151
935279293151
SC16IS762IBS-S
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SC16IS762IBS,151 Summary of contents
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SC16IS752/SC16IS762 Dual UART with I and receive FIFOs, IrDA SIR built-in support Rev. 07 — 19 May 2008 1. General description The SC16IS752/SC16IS762 performance UART offering data rates Mbit/s, low operating and sleeping current; ...
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... NXP Semiconductors I RS-485 driver direction control inversion I Built-in IrDA encoder and decoder supporting IrDA SIR with speeds up to 115.2 kbit/s I SC16IS762 supports IrDA SIR with speeds up to 1.152 Mbit/s I Software reset I Transmitter and receiver can be enabled/disabled independent of each other I Receive and Transmit FIFO levels ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name SC16IS752IPW TSSOP28 SC16IS762IPW SC16IS752IBS HVQFN32 SC16IS762IBS SC16IS752_SC16IS762_7 Product data sheet Dual UART with I Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; ...
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... NXP Semiconductors 5. Block diagram SPI interface Fig 1. SC16IS752_SC16IS762_7 Product data sheet Dual UART with SC16IS752/ SC16IS762 SDA SCL C-BUS 1 k (3.3 V) 1.5 k (2.5 V) IRQ RESET V DD I2C/SPI XTAL1 XTAL2 2 C-bus interface V DD SC16IS752/ SC16IS762 SCLK SPI 1 k (3.3 V) 1.5 k (2.5 V) IRQ ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning RTSA 1 2 CTSA 3 TXA RXA 4 RESET 5 6 XTAL1 XTAL2 7 SC16IS752IPW SC16IS762IPW I2C n. SCL SDA 14 002aab657 C-bus interface Fig 2. Pin configuration for TSSOP28 terminal 1 index area RXA 1 RESET 2 3 XTAL1 XTAL2 4 SC16IS752IBS SC16IS762IBS I2C 7 A0 ...
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... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin TSSOP28 HVQFN32 CS/ CTSA 2 31 CTSB 16 15 I2C/SPI 9 6 IRQ 15 14 SI/ SCL/SCLK 13 10 SDA 14 11 GPIO0/DSRB 18 17 GPIO1/DTRB 19 18 GPIO2/CDB 20 19 GPIO3/RIB 21 20 GPIO4/DSRA 25 24 GPIO5/DTRA 26 25 GPIO6/CDA 27 26 GPIO7/RIA 28 27 SC16IS752_SC16IS762_7 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TSSOP28 HVQFN32 RESET 5 2 RTSA 1 30 RTSB 17 16 RXA 4 1 RXB 24 23 TXA 3 32 TXB 13 12, 21 center SS pad XTAL1 6 3 XTAL2 7 4 [1] Selectable with IOControl register bit 2. [2] Selectable with IOControl register bit 1. ...
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... NXP Semiconductors 7. Functional description The UART will perform serial-to-I peripheral devices or modems, and I transmitted by the host. The complete status of the SC16IS752/SC16IS762 UART can be read at any time during functional operation by the host. The SC16IS752/SC16IS762 can be placed in an alternate mode (FIFO mode) relieving the host of excessive software overhead by buffering received/transmitted characters ...
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... NXP Semiconductors Fig 4. 7.2.1 Auto-RTS Figure 5 are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The sending device (for example, another UART) may send an additional character after the ...
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... NXP Semiconductors 7.2.2 Auto-CTS Figure 6 sending the next data character. When CTS is active, the transmitter sends the next character. To stop the transmitter from sending the following character, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The Auto-CTS function reduces interrupts to the host system. When fl ...
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... NXP Semiconductors There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Receiving any character will resume operation after recognizing the Xoff character possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. • ...
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... NXP Semiconductors Fig 7. SC16IS752_SC16IS762_7 Product data sheet Dual UART with I UART1 TRANSMIT FIFO PARALLEL-TO-SERIAL Xoff–Xon–Xoff SERIAL-TO-PARALLEL Xon1 WORD Xon2 WORD Xoff1 WORD Xoff2 WORD Example of software flow control Rev. 07 — 19 May 2008 SC16IS752/SC16IS762 2 C-bus/SPI interface, 64-byte FIFOs, IrDA SIR ...
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... NXP Semiconductors 7.4 Hardware Reset, Power-On Reset (POR) and Software Reset These three reset methods are identical and will reset the internal registers as indicated in Table 4. Table 4 Table 4. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register ...
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... NXP Semiconductors 7.5 Interrupts The SC16IS752/SC16IS762 has interrupt generation and prioritization (seven prioritized levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable each of the seven types of interrupts and the IRQ signal in response to an interrupt generation. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0] ...
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... NXP Semiconductors 7.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3: the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Fig 8. ...
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... NXP Semiconductors 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS752/SC16IS762 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data input line, RX, is idle (see conditions”). • ...
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... NXP Semiconductors Figure 10 XTAL1 XTAL2 Fig 10. Prescaler and baud rate generator block diagram DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled baud clock will be generated ...
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... NXP Semiconductors Table 8. Desired baud rate (bit/ 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 Fig 11. Crystal oscillator circuit reference SC16IS752_SC16IS762_7 Product data sheet 2 Dual UART with I Baud rates using a 3.072 MHz crystal Divisor used to generate ...
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... NXP Semiconductors 8. Register descriptions The programming combinations for register selection are shown in Table 9. Register name Read mode RHR/THR IER IIR/FCR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL IODir IOState IOIntEna IOControl EFCR DLL DLH EFR XON1 XON2 XOFF1 XOFF2 [1] MCR[7] can only be modifi ...
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Table 10. SC16IS752/SC16IS762 internal registers Register Register Bit 7 Bit 6 address [1] General register set 0x00 RHR bit 7 bit 6 0x00 THR bit 7 bit 6 0x01 IER CTS interrupt RTS interrupt [2] enable enable 0x02 FCR RX ...
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Table 10. SC16IS752/SC16IS762 internal registers Register Register Bit 7 Bit 6 address [9] Special register set 0x00 DLL bit 7 bit 6 0x01 DLH bit 7 bit 6 [10] Enhanced register set 0x02 EFR Auto CTS Auto RTS 0x04 XON1 ...
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... NXP Semiconductors 8.1 Receive Holding Register (RHR) The receiver section consists of the Receive Holding Register (RHR) and the Receive Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register ...
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... NXP Semiconductors Table 11. Bit 1 0 [1] IER[7:4] can only be modified if EFR[4] is set, that is, EFR[ write enable. Re-enabling IER[1] will not cause a new interrupt if the THR is below the threshold. 8.4 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels ...
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... NXP Semiconductors 8.5 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 13. Bit 7:6 5:1 0 Table 14. Priority level [1] Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState register ...
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... NXP Semiconductors Table 15. Bit 1:0 Table 16. LCR[ Table 17. LCR[ Table 18. LCR[ SC16IS752_SC16IS762_7 Product data sheet Dual UART with I Line Control Register bits description Symbol Description LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = logic 1). logic 0 = parity is not forced (normal default condition). ...
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... NXP Semiconductors 8.7 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 19. Bit [1] MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[ write enable. SC16IS752_SC16IS762_7 Product data sheet ...
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... NXP Semiconductors 8.8 Line Status Register (LSR) Table 20 Table 20. Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). Therefore, errors in a character are identified by reading the LSR and then reading the RHR. ...
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... NXP Semiconductors 8.9 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the modem changes state. channel. Table 21. ...
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... NXP Semiconductors 8.11 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. settings. If TCR bits are cleared, then selectable trigger levels in FCR are used in place of TCR. Table 22. Bit 7:4 3:0 TCR trigger levels are available from 0 bytes to 60 characters with a granularity of four. ...
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... NXP Semiconductors 8.13 Transmitter FIFO Level register (TXLVL) This register is a read-only register. It reports the number of spaces available in the transmit FIFO. Table 24. Bit 7 6:0 8.14 Receiver FIFO Level register (RXLVL) This register is a read-only register, it reports the fill level of the receive FIFO, that is, the number of characters in the RX FIFO ...
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... NXP Semiconductors 8.17 I/O Interrupt Enable register (IOIntEna) This register enables the interrupt due to a change in the I/O configured as inputs. If GPIO[7:4] or GPIO[3:0] are programmed as modem pins, their interrupt generation must be enabled via IER[3]. In this case, IOIntEna will have no effect on GPIO[7:4] or GPIO[3:0] ...
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... NXP Semiconductors 8.19 Extra Features Control Register (EFCR) Table 30. Bit [1] For SC16IS762 only. 8.20 Division registers (DLL, DLH) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores the least signifi ...
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... NXP Semiconductors 8.21 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. the Enhanced Features Register bit settings. Table 31. Bit 3:0 9. RS-485 features 9.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR bit hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware fl ...
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... NXP Semiconductors 9.3 Auto RS-485 EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of operation, a ‘master’ station transmits an address character followed by data characters for the addressed ‘slave’ stations. The slave stations examine the received data and interrupt the controller if the received character is an address character (parity bit = 1). To use the auto RS-485 RTS mode the software would have to disable the hardware fl ...
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... NXP Semiconductors 2 10. I C-bus operation The two lines of the I lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device ...
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... NXP Semiconductors SDA MSB SCL START condition 2 Fig 14. Data transfer on the I data output by transmitter data output by receiver SCL from master S START condition 2 Fig 15. Acknowledge on the I A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter ...
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... NXP Semiconductors 10.2 Addressing and transfer formats Each device on the bus has its own unique address. Before any data is transmitted on the bus, the master transmits on the bus the address of the slave to be accessed for this transaction. A well-behaved slave with a matching address exists on the network, should of course acknowledge the master's addressing. The addressing is done by the fi ...
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... NXP Semiconductors In a single master system, the ‘Repeated START’ mechanism may be more efficient than terminating each transfer with a STOP and starting again multimaster environment, the determination of which format is more efficient could be more complicated, as when a master is using repeated STARTs occupies the bus for a long time, and thus preventing other devices from initiating transfers ...
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... NXP Semiconductors 10.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. address can be selected by using A1 and A0 pins. For example, if these 2 pins are connected to V master communicates with it through this address ...
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... NXP Semiconductors S SLAVE ADDRESS White block: host to SC16IS752/SC16IS762 Grey block: SC16IS752/SC16IS762 to host (1) See Table 33 for additional information. Fig 18. Master writes to slave The register read cycle (see sending a slave address with the direction bit set to WRITE with a following subaddress. Then, in order to reverse the direction of the transfer, the master issues a Repeated START followed again by the device address, but this time with the direction bit set to READ ...
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SCLK CH1 CH0 X SI R/W R A[3:0] = register address; CH[1: for channel A; CH[1: for channel B a. Register write SCLK SI R CH1 ...
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... NXP Semiconductors Table 34. Bit 7 6:3 2:1 0 12. Limiting values Table 35. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot P/out T amb stg [1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. ...
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... NXP Semiconductors 13. Static characteristics Table 36. Static characteristics V = 2 amb Symbol Parameter Supplies V supply voltage DD I supply current DD Inputs I2C/SPI, RX, CTS V HIGH-level input voltage IH V LOW-level input voltage IL I leakage current L C input capacitance i Outputs TX, RTS HIGH-level output voltage OH V LOW-level output voltage ...
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... NXP Semiconductors Table 36. Static characteristics V = 2 amb Symbol Parameter 2 I C-bus inputs SCL, CS/A0, SI/A1 V HIGH-level input voltage IH V LOW-level input voltage IL I leakage current L C input capacitance i [2] Clock input XTAL1 V HIGH-level input voltage IH V LOW-level input voltage IL I leakage current ...
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... NXP Semiconductors 14. Dynamic characteristics 2 Table 37. I C-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load 2 amb voltage All output load = 25 pF, except SDA output load = 400 pF. ...
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... NXP Semiconductors RESET Fig 21. SCL delay after reset START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 22. I C-bus timing diagram SDA GPIOn Fig 23. Write to output SLAVE ADDRESS SDA IRQ MODEM pin Fig 24. Modem input pin interrupt ...
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... NXP Semiconductors SLAVE ADDRESS SDA IRQ GPIOn Fig 25. GPIO pin interrupt RX IRQ Fig 26. Receive interrupt SLAVE ADDRESS SDA IRQ Fig 27. Receive interrupt clear SLAVE ADDRESS SDA IRQ Fig 28. Transmit interrupt clear SC16IS752_SC16IS762_7 Product data sheet Dual UART with I ACK from slave ...
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... NXP Semiconductors Table 38. f dynamic characteristics XTAL V = 2 amb Symbol Parameter t clock pulse duration w1 t clock pulse duration w2 f oscillator/clock frequency XTAL [1] Applies to external clock, crystal oscillator max. 24 MHz ------- [2] XTAL t w3 EXTERNAL CLOCK Fig 29. External clock timing SC16IS752_SC16IS762_7 Product data sheet ...
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... NXP Semiconductors Table 39. SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load 2 amb voltage All output load = 25 pF, unless otherwise specified Symbol Parameter t CS HIGH to SO 3-state ...
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... NXP Semiconductors CS SCLK R/W GPIOx R A[3:0] = IOState (0x0B); CH[1: for channel A; CH[1: for channel B Fig 31. SPI write IOState to GPIO switch CS SCLK SI A3 R/W DTR (GPIO5) R A[3:0] = MCR (0x04); CH[1: for channel A; CH[1: for channel B Fig 32. SPI write MCR to DTR output switch ...
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... NXP Semiconductors CS SCLK R/W SO IRQ R A[3:0] = MSR (0x06); CH[1: for channel A; CH[1: for channel B Fig 34. Read MSR to clear modem interrupt CS SCLK R/W SO IRQ R A[3:0] = IOState (0x0B); CH[1: for channel A; CH[1: for channel B Fig 35. Read IOState to clear GPIO interrupt CS SCLK R/W SO IRQ R ...
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... NXP Semiconductors 15. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 39. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 42. Acronym CPU DLL DLH FIFO GPIO 2 I C-bus IrDA LCD MIR POR ...
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... NXP Semiconductors 19. Revision history Table 43. Revision history Document ID Release date SC16IS752_SC16IS762_7 20080519 • Modifications: • • • • • • • • SC16IS752_SC16IS762_6 20061219 SC16IS752_SC16IS762_5 20061128 SC16IS752_SC16IS762_4 20061013 SC16IS752_SC16IS762_3 20060707 SC16IS752_SC16IS762_2 20060330 SC16IS752_SC16IS762_1 20060104 (9397 750 14333) SC16IS752_SC16IS762_7 Product data sheet ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.2 I C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 8 7.1 Trigger levels 7.2 Hardware flow control . . . . . . . . . . . . . . . . . . . . 8 7 ...