STA2500DC

Manufacturer Part NumberSTA2500DC
ManufacturerSTMicroelectronics
STA2500DC datasheets

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Specifications of STA2500DC

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STA2500D
Figure 18. SPI setup and hold timing
Table 25.
SPI timing parameters
Symbol
P
SPI_CLK full period
CL
T
High period of SPI_CLK
CLH
T
Low period of SPI_CLK
CLL
T
High period of SPI_CSN
CSH
T
Low period of SPI_CSN
CSL
T
Setup time, SPI_CSN Low to SPI_CLK high
SCS
T
Setup time, SPI_CLK Low to SPI_CSN high
SCL
T
Setup time, SPI_MOSI valid to SPI_CLK high
SDC
Hold time, SPI_MOSI valid after SPI_CLK
T
HCD
high
T
Setup time, SPI_CLK Low to SPI_MISO valid
SCLD
7.3
The PCM interface
The chip contains a 4-pin direct voice interface to connect to standard CODEC.
The interface supports multiport PCM operations for voice transfer. It can be programmed to
act as a Master or a Slave via a SW parameter download or via specific HCI commands.
The four signals of the multiport PCM interface are:
●
PCM_CLK
PCM_SYNC : PCM 8 kHz sync (every 125 μs)
●
●
PCM_A
●
PCM_B
As a Master the interface by default generates a PCM clock rate of 2048 kHz, but it can be
configured to rates from 8 kHz up to 2048 kHz. As a Slave, it can automatically handle
external PCM clock rates from 128 kHz up to 4000 kHz. The default PCM_SYNC rate is 8
kHz.
The following external PCM data format are supported: linear (13 - 16 bit), µ−law (8 bit) or A-
law (8 bit).
S PI_C SN
T
SPI_CLK
S CS
S PI_D I
S PI_D O
Description
: PCM clock
: PCM data (TX or RX)
: PCM data (RX or TX)
Doc ID 16067 Rev 2
Digital interfaces
T
T
C SL
CSH
P
CL
T
T
S CL
CLL
T
CLH
T
T
SDC
HCD
T
SC LD
Min.
Typ.
Max.
70
0
0
16.6
26.4
1 * P
CL
9 * P
CL
1 * P
CL
1
/
* P
2
CL
9.7
5
0
26.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43/58

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