SC16C850IBS,157 NXP Semiconductors, SC16C850IBS,157 Datasheet
SC16C850IBS,157
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SC16C850IBS,157 Summary of contents
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SC16C850 2 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface Rev. 2 — 11 November 2010 1. General description The SC16C850 ...
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... NXP Semiconductors Programmable Xon/Xoff characters Software selectable baud rate generator Support IrDA version 1.0 (up to 115.2 kbit/s) Standard modem interface or infrared IrDA encoder/decoder interface Enhanced Sleep mode and low power feature Modem control functions (CTS, RTS, DSR, DTR, RI, CD) Independent transmitter and receiver enable/disable Pb-free, RoHS compliant package offered 3 ...
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... NXP Semiconductors 4. Block diagram SC16C850 DATA BUS IOR IOW CONTROL RESET REGISTER POWER-DOWN LOWPWR CONTROL INTERRUPT INT CONTROL Fig 1. Block diagram of SC16C850 (16 mode) SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder AND LOGIC SELECT LOGIC LOGIC XTAL1 All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors SC16C850 DATA BUS R/W CONTROL RESET REGISTER POWER-DOWN LOWPWR CONTROL INTERRUPT IRQ CONTROL Fig 2. Block diagram of SC16C850 (68 mode) SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder AND LOGIC SELECT LOGIC LOGIC XTAL1 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 3. Fig 4. SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder ball A1 index area Pin configuration for TFBGA36 n. n. INT RTS E DTR n.c. F RESET DSR Transparent top view. Ball mapping for TFBGA36 All information provided in this document is subject to legal disclaimers. Rev. 2 — ...
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... NXP Semiconductors terminal 1 index area SC16C850IBS D6 4 SC16C850IBS/Q900 D7 5 (16 mode Transparent top view a. 16 mode Fig 5. Pin configuration for HVQFN32 5.2 Pin description Table 2. Pin description Symbol Pin TFBGA36 HVQFN32 16/ CTS D3 24 DSR F2 25 DTR E1 22 SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TFBGA36 HVQFN32 INT - 20 (IRQ) INT D1 - IOR - IOR A3 - IOW - 12 (R/W) IOW B4 - LOWPWR B5 9 RESET - 23 (RESET) RESET SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Type Description I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TFBGA36 HVQFN32 RTS A1 [ XTAL1 A6 10 XTAL2 A5 11 [1] HVQFN32 package die supply ground is connected to both V ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors 6. Functional description The SC16C850 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol) ...
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... NXP Semiconductors Table HIGH LOW. Chip Select 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. 6.3 Internal registers The SC16C850 provides a set of 25 internal registers for monitoring and controlling the functions of the UART ...
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... NXP Semiconductors Table Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1 [1] These registers are accessible only when LCR[ logic 0. [2] These registers are accessible only when LCR[ logic 1. [3] Second Special registers are accessible only when EFCR[ [4] Enhanced Feature Registers are only accessible when LCR = 0xBF. ...
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... NXP Semiconductors 6.5 Hardware flow control When automatic hardware flow control is enabled, the SC16C850 monitors the CTS pin for a remote buffer overflow indication and controls the RTS pin for local buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS logic 1 ...
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... NXP Semiconductors Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions (see SC16C850 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly ...
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... NXP Semiconductors each time the Receive Holding Register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times. 6.9 Programmable baud rate generator ...
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... NXP Semiconductors Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in shows the selectable baud rate table available when using a 1.8432 MHz external clock input when MCR[ and CLKPRES = 0x00. ...
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... NXP Semiconductors Table 7. Output baud rate (bit/s) 38.4 k 57.6 k 115.2 k 6.10 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally (see Figure In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally ...
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... NXP Semiconductors SC16C850 DATA BUS AND IOR CONTROL IOW LOGIC RESET REGISTER SELECT CS LOGIC POWER- LOWPWR DOWN CONTROL INTERRUPT INT CONTROL (IRQ) LOGIC Fig 9. Internal Loopback mode diagram SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C850 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] bit is set. 6.11.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. ...
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... NXP Semiconductors 6.13 RS-485 features 6.13.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR[1 hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. AFCR2[4] will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin ...
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... NXP Semiconductors 6.13.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the Xoff2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the Xoff2 register, the receiver will discard these data ...
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Table 8. SC16C850 internal registers [ Register Default Bit 7 [2] General register set RHR 0xXX bit THR 0xXX bit IER 0x00 CTS [3] interrupt 0 ...
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Table 8. SC16C850 internal registers …continued [ Register Default Bit 7 [5] Enhanced feature register set EFR 0x00 Auto CTS Xon1 0x00 bit Xon2 0x00 bit 15 ...
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... NXP Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the transmit FIFO ...
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... NXP Semiconductors Table 9. Bit Symbol Description 1 IER[1] 0 IER[0] 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO trigger levels. 7.3.1 FIFO mode Table 10. Bit 7:6 5 [1] For 128-byte FIFO mode, refer to [2] For 128-byte FIFO mode, refer to Table 11 ...
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... NXP Semiconductors Table 12. FCR[ [1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see 7.4 Interrupt Status Register (ISR) The SC16C850 provides six levels of prioritized interrupts to minimize external software interaction ...
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... NXP Semiconductors Table 14. Bit 0 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15. Bit 7 6 5:3 ...
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... NXP Semiconductors Table 18. LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Bit SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder LCR[1:0] word length LCR[0] Word length (bits) ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C850 and the CPU. Table 20. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C850 is connected. Four bits of this register are used to indicate the changed information ...
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... NXP Semiconductors 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: ‘first extra feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). ...
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... NXP Semiconductors 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers ...
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... NXP Semiconductors Table 24. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level Register (TXINTLVL) This 8-bit register is used to store the transmit FIFO trigger levels used for interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. ...
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... NXP Semiconductors [1] For 32-byte FIFO mode, refer to 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. register bit settings; see Table 27. Bit 7:0 [1] For 32-byte FIFO mode, refer to 7 ...
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... NXP Semiconductors 7.20 RS-485 Turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode RTS or DTR pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register ...
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... NXP Semiconductors 7.22 Advanced Feature Control Register 1 (AFCR1) Table 32. Bit 7 [1] It takes 4 XTAL1 clocks to reset the device. SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Advanced Feature Control Register 1 register bits description Symbol Description AFCR1[7:5] reserved AFCR1[4] Sleep RXLow ...
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... NXP Semiconductors 7.23 SC16C850 external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 33. Table 33. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 ...
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... NXP Semiconductors 8. Limiting values Table 35. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P /pack tot 9. Static characteristics Table 36. Static characteristics − ° ° +85 C; tolerance of V amb Symbol Parameter V clock LOW-level input voltage IL(clk) V clock HIGH-level input voltage ...
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... NXP Semiconductors 10. Dynamic characteristics Table 37. Dynamic characteristics - Intel or 16 mode − ° ° +85 C; tolerance of V amb Symbol Parameter t pulse width HIGH WH t pulse width LOW WL t clock pulse width w(clk) f frequency on pin XTAL1 XTAL1 t address set-up time su(A) t address hold time ...
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... NXP Semiconductors Table 38. Dynamic characteristics - Motorola or 68 mode − ° ° +85 C; tolerance of V amb Symbol Parameter t pulse width HIGH WH t pulse width LOW WL t clock pulse width w(clk) f frequency on pin XTAL1 XTAL1 t address set-up time su(A) t address hold time h(A) ...
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... NXP Semiconductors 10.1 Timing diagrams su( d(CSL-IOWL) IOW Fig 10. General write timing (16 mode su( su(RWL-CSL) R Fig 11. General write timing (68 mode) SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder t h(A) valid address t h(IOW-CS) active t t w(IOW) d(IOW) active t h(IOWH-D) ...
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... NXP Semiconductors su( d(CS-IOR) IOR Fig 12. General read timing (16 mode su( su(RWH-CSL) R Fig 13. General read timing (68 mode) external clock 1 -------------- - f = XTAL clk Fig 14. External clock timing SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder t h(A) valid address t h(IOR-CS) ...
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... NXP Semiconductors IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 15. Modem input/output timing (16 mode) (1) CS (write) RTS change of state DTR CD CTS DSR IRQ (2) CS (read) RI (1) CS timing during a write cycle. See (2) CS timing during a read cycle. See Fig 16. Modem input/output timing (68 mode) ...
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... NXP Semiconductors RX (1)(2) INT IOR (1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see (2) INT is cleared when RX FIFO drops below trigger level. Fig 17. Receive timing in 16 mode RX (1)(2) IRQ CS (read) (1) IRQ is active when RX FIFO fills up to trigger level or time-out condition happens (see (2) IRQ is cleared when RX FIFO drops below trigger level ...
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... NXP Semiconductors TX (1)(2) INT active IOW (1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level. (2) INT is cleared when ISR is read or TX FIFO fills up to trigger level. Fig 19. Transmit timing in 16 mode TX (1)(2) IRQ t d(CS-TX)W active CS (write) (1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level. ...
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... NXP Semiconductors IrDA TX data Fig 21. Infrared transmit timing IrDA RX data RX data Fig 22. Infrared receive timing SC16C850 Product data sheet 2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder start TX data bit time bit time start All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 11. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.90 0.35 mm 1.15 0.15 0.75 0.25 OUTLINE VERSION IEC - - - SOT912-1 Fig 24. Package outline SOT912-1 (TFBGA36) ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 41. Acronym CPU DLL DLM FIFO IrDA ISDN LSB MSB PCB RoHS UART SC16C850 Product data sheet 2 ...
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... NXP Semiconductors 14. Revision history Table 42. Revision history Document ID Release date SC16C850 v.2 20101111 • Modifications: Table 1 “Ordering – added Type number SC16C850IBS/Q900 – added Table note [1] • Figure 5 “Pin configuration for • Table 2 “Pin pull-down resistor, ...” to “This pin has a 22 kΩ internal pull-down resistor, ...” ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... V UART with 128-byte FIFOs and IrDA encoder/decoder NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 UART selection 6.2 Extended mode (128-byte FIFO 6.3 Internal registers . . . . . . . . . . . . . . . . . . . . . . . 10 6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4.1 32-byte FIFO mode ...