MAX3100CEE Maxim Integrated Products, MAX3100CEE Datasheet - Page 11

IC UART SPI/MICRWIRE COMP 16QSOP

MAX3100CEE

Manufacturer Part Number
MAX3100CEE
Description
IC UART SPI/MICRWIRE COMP 16QSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX3100CEE

Features
Low Power
Number Of Channels
1, UART
Fifo's
8 Byte
Protocol
RS232, RS485
Voltage - Supply
2.7 V ~ 5.5 V
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
16-SSOP (0.150", 3.90mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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A Read Data operation clears the interrupt IRQ. Table
6 gives the details for each interrupt source. Figure 6
Table 6. Interrupt Sources and Masks—Bit Descriptions
Figure 6. Interrupt Sources and Masks Functional Diagram
NAME
RA/FE
BIT
Pr
R
T
MASK
IRQ
RAM
BIT
PM
RM
TM
N
Interrupt Sources and Masks
______________________________________________________________________________________
Received parity bit = 1
Data available
Transition on RX when
in shutdown; framing
error when not in
shutdown
Transmit buffer is
empty
WHEN SET
MEANING
The Pr bit reflects the value in the word currently in the receive-buffer register
(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the
received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE
= 0), or when parity is enabled and the received bit is 0. An interrupt is issued
based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next
value that will be read by a Read Data operation.
The R bit is set when new data is available to be read from the receive register/
FIFO. FIFO is cleared when all data has been read. An interrupt is asserted as long
as R = 1 and RM = 1.
This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in
operating mode. RA is set if there has been a transition on RX since entering
shutdown. RA is cleared when the MAX3100 exits shutdown. IRQ is asserted
when RA is set and RAM = 1.
FE is determined solely by the currently received data, and is not stored in FIFO.
The FE bit is set if a zero is received when the first stop bit is expected. FE is
cleared upon receipt of the next properly framed character. IRQ is asserted
when FE is set and RAM = 1.
The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted
low if TM = 1 and the transmit buffer becomes empty. This source is cleared on
CS’s rising edge during a Read Data operation. Although the interrupt is cleared,
T may be polled to determine transmit-buffer status.
SPI/MICROWIRE-Compatible
T
Pr
RA
FE
R
shows the functional diagram for the interrupt sources
and mask blocks.
RM MASK
TM MASK
PM MASK
TRANSITION ON RX
RAM MASK
FRAMING ERROR
RAM MASK
Q
Q
Q
DESCRIPTION
UART in QSOP-16
S
R
S
R
S
R
NEW DATA AVAILABLE
DATA READ
TRANSMIT BUFFER EMPTY
DATA READ
PE = 1 AND RECEIVED PARITY BIT = 1
PE = 0 OR RECEIVED PARITY BIT = 0
SHUTDOWN
SHUTDOWN
11

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