FW802B-DB LSI, FW802B-DB Datasheet
FW802B-DB
Specifications of FW802B-DB
Related parts for FW802B-DB
FW802B-DB Summary of contents
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... Multiple separate package signals provided for ana- log and digital supplies and grounds. Description The Agere Systems Inc. FW802B device provides the analog physical layer functions needed to imple- ment a two-port node in a cable-based IEEE 1394- 1995 and IEEE 1394a-2000 network. ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Contents Distinguishing Features ...............................................................................................................................................1 Features ......................................................................................................................................................................1 Other Features ............................................................................................................................................................1 Description ..................................................................................................................................................................1 Signal Information .......................................................................................................................................................6 Application Information ..............................................................................................................................................11 Crystal Selection Considerations ..............................................................................................................................12 Load Capacitance ..............................................................................................................................................13 Adjustment to Crystal Loading ...........................................................................................................................13 Crystal/Board Layout ..........................................................................................................................................13 1394 Application Support Contact Information ..........................................................................................................13 Absolute Maximum Ratings .......................................................................................................................................14 Electrical Characteristics ...........................................................................................................................................15 Timing Characteristics ...............................................................................................................................................18 Timing Waveforms ...
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... IEEE 1394-1995 Annex J. To operate with bus-keeper isolation, the /ISO pin of the FW802B must be tied high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49 ...
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... Table 11) cleared. The FW802B will exit the low-power mode when the LPS input is asserted high or when a port event occurs that requires the FW802B to become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias or disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc ...
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... CTL0 INTERFACE I/O CTL1 PC0 PC1 PC2 C/LKON /RESET Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device RECEIVED DATA VOLTAGE DECODER/ RETIMER CURRENT GENERATOR ARBITRATION AND CONTROL STATE MACHINE LOGIC CABLE PORT 0 CABLE PORT 1 TRANSMIT DATA ENCODER CRYSTAL ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Signal Information LREQ CTL0 3 CTL1 CNA 15 LPS 16 Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document PIN #1 IDENTIFIER AGERE FW802B Figure 2. Pin Assignments Data Sheet, Rev. 3 May 2004 ...
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... After hardware reset, this pin is set as an output. If the LPS is inactive, C/LKON indicates one of the following events by asserting a 6.114 MHz signal. 1. FW802B receives a link-on packet addressed to this node. 2. Port_event register bit Any of the Timeout, Pwr_fail, or Loop register bits are 1 and the Watchdog register bit is also 1 ...
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... PC0 = 0, PC1 = 0, and PC2 = 1. Powerdown. When asserted high, PD turns off all internal circuitry except the bias-detect circuits that drive the CNA signal. Internal FW802B logic is kept in the reset state as long asserted. The PD terminal is provided for backward compatibility recommended that the FW802B be allowed to manage its own power consumption using suspend/resume in conjunction with LPS ...
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... Name/Description Reset (Active-Low). When /RESET is asserted low (active), a 1394 bus reset condition is set on the active cable ports and the FW802B is reset to the reset start state. To guarantee that the PHY will reset, this pin must be held low for at least 2 ms. An internal pull-up resistor connected to V provided so that only an external delay capacitor (0.1 µ ...
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... V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW802B’s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected ...
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... LLC CNA 15 LPS LLC PULSE See Figure 4 for typical port termination network. Figure 3. Typical External Component Connections Agere Systems Inc. Two-Cable Transceiver/Arbiter Device PIN #1 IDENTIFIER AGERE FW802B DDA 43 TPBIAS1 42 TPA1+ 41 TPA1– PORT 1* 40 TPB1+ 39 TPB1– 38 TPBIAS0 37 TPA0+ 36 TPA0– ...
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... XI and XO terminals to provide the reference for an internal oscillator circuit. The IEEE 1394a-2000 standard requires that FW802B have less than ±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. The total frequency variation must be kept below ± ...
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... Load Capacitance The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. Total load capacitance (C capacitances from the FW802B board traces and capacitances of the other FW802B connected components. The values for load capacitors ( × 2 ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet ...
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... TPBIAS Output Voltage Current Source for Connect Detect Circuit * For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard). Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Test Conditions Source power node TPB cable inputs, ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Electrical Characteristics Table 4. Driver Characteristics Parameter Differential Output Voltage Off-state Common-mode Voltage Driver Differential Current, TPA+, TPA−, TPB+, TPB− Common-mode Speed Signaling Current, TPB+, TPB− * Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− as the algebraic sum of driver currents. † ...
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... Falling Input Threshold Voltage*, LREQ, CTLn, Dn Bus Holding Current, LREQ, CTLn, Dn Rising Input Threshold Voltage LPS Falling Input Threshold Voltage LPS * Device is capable of both differentiated and undifferentiated operation. Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device (continued) Test Conditions Symbol ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Timing Characteristics Table 6. Switching Characteristics Symbol Parameter — Jitter, Transmit — Transmit Skew t Rise Time, Transmit (TPA/TPB Fall Time, Transmit (TPA/TPB Setup Time, su Dn, CTLn, LREQ↑↓ to SYSCLK↑ t Hold Time, h Dn, CTLn, LREQ↑↓ from SYSCLK↑ ...
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... Data Sheet, Rev. 3 May 2004 Timing Waveforms Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device SYSCLK tsu Dn, CTLn, LREQ SYSCLK ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Internal Register Configuration The PHY register map is shown below in Table 8. (Refer to IEEE 1394a-2000, 5B.1 for more information). Table 8. PHY Register Map for the Cable Environment Address Bit 0 Bit 1 0000 2 0001 RHB IBR 2 0010 ...
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... Pwr_fail 1 rw Timeout 1 rw Port_event 1 rw Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device (continued) 2 The number of ports implemented by this PHY. This count reflects the number. 010 Indicates the speed(s) this PHY supports: 2 000 = 98.304 Mbits/s 2 001 = 98 ...
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... FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device Internal Register Configuration Table 9. PHY Register Fields for the Cable Environment (continued) Field Size Type Power Reset Enab_accel 1 rw Enab_multi 1 rw Page_select 3 rw Port_select 4 rw The port status page is used to access configuration and status information for each of the PHY’s ports. The port is ...
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... Connected 1 r Bias 1 r Disabled 1 rw Negotiated_speed 3 r Int_enable 1 rw Fault 1 rw Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device (continued) Power Reset Value — TPA line state for the port invalid — TPB line state for the port (same encoding as AStat). ...
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... Table 13. PHY Register Vendor Identification Page Fields Field Size Type Compliance_level 8 r Vendor_ID 24 r Product_ID 24 r The vendor-dependent page provides access to information used in manufacturing test of the FW802B. 24 (continued) . The format of the vendor identification page is 2 Contents Bit 2 Bit 3 Bit 4 Compliance_level Vendor_ID Product_ID ...
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... DETAIL B 0.50 TYP Ordering Information Device Code FW802B-DB 64-Pin TQFP L-FW802B-DB 64-Pin TQFP (lead-free effort to better serve its customers and the environment, Agere is switching to lead-free packaging on this product (no intentional addition of lead). Agere Systems Inc. FW802B Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device ...
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