IS43DR16320B-3DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16320B-3DBLI Datasheet - Page 10

• Manufacturer Part Number: IS43DR16320B-3DBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16320B-3DBLI

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 280mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR86400B, IS43/46DR16320B
Clock Enable (CKE) Truth Table
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Power Down and Self Refresh cannot be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations are in
11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in this
14. CKE must be maintained HIGH while the DDRII SDRAM is in OCD calibration mode.
15. “X” means “Don’t Care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT
16. VREF must be maintained during Self Refresh operation.
Data Mask (DM) Truth Table
Note:
1.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
Current State
Bank(s) Active
All Banks Idle
Power Down
Self Refresh
CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
On Self Refresh Exit, DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only
after tXSRD (200 clocks) is satisfied.
Self Refresh mode can only be entered from the All Banks Idle state.
Must be a legal command as defined in the Command Truth Table.
Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
Valid commands for Self Refresh Exit are NOP and DESELECT only.
progress.
achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.
datasheet.
function is enabled (Bit A2 or A6 set to “1” in EMR[1]).
Used to mask write data, provided coincident with the corresponding data.
Name (Functional)
Write Enable
Write Inhibit
(2)
Previous Cycle
H
H
H
H
L
L
L
L
(1)
(N-1)
CKE
Current Cycle
DM
H
L
H
H
H
L
L
L
L
L
(1)
(N)
RAS#, CAS#, WE#, CS#
Deselect or NOP
Deselect or NOP
Deselect or NOP
Deselect or NOP
Command (N)
Refresh
X
X
Refer to the Command Truth Table
(3)
Valid
DQs
X
Precharge Power Down Entry
Active Power Down Entry
Maintain Power-Down
Maintain Self-Refresh
Self-Refresh Entry
Power Down Exit
Self-Refresh Exit
Action (N)
(3)
Note
1
1
4, 8, 10, 11, 13
4, 8, 10, 11, 13
4, 8, 11, 13
6, 9, 11, 13
11, 13, 15
11, 15, 16
4, 5, 9, 16
Notes
7
10