CS4525-CNZ Cirrus Logic Inc, CS4525-CNZ Datasheet

IC AMP AUDIO PWR 30W QUAD 48QFN

CS4525-CNZ

Manufacturer Part Number
CS4525-CNZ
Description
IC AMP AUDIO PWR 30W QUAD 48QFN
Manufacturer
Cirrus Logic Inc
Series
Popguard®r
Type
Class Dr
Datasheet

Specifications of CS4525-CNZ

Output Type
2-Channel (Stereo) or 4-Channel (Quad)
Package / Case
48-QFN
Max Output Power X Channels @ Load
30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
Voltage - Supply
8 V ~ 18 V
Features
ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
Mounting Type
Surface Mount
Product
Class-D
Output Power
30 W
Thd Plus Noise
10 %
Operating Supply Voltage
2.5 V to 5 V
Supply Current
54 mA
Maximum Power Dissipation
180 mW
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Audio - Load Impedance
4 Ohms, 6 Ohms, 8 Ohms
Audio Load Resistance
8 Ohms, 4 Ohms
Minimum Operating Temperature
0 C
Supply Voltage (max)
5.25 V
Supply Voltage (min)
2.375 V
Amplifier Class
D
No. Of Channels
4
Supply Voltage Range
8V To 18V
Load Impedance
4ohm
Operating Temperature Range
0°C To +70°C
Amplifier Case Style
QFN
No. Of Pins
48
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1586 - REFERENCE BOARD FOR CS4525 PWM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1264

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4525-CNZ
Manufacturer:
CRYSTAL
Quantity:
329
Part Number:
CS4525-CNZ
Manufacturer:
TI/德州仪器
Quantity:
20 000
Part Number:
CS4525-CNZ
Manufacturer:
CIRRUS
Quantity:
4 034
Part Number:
CS4525-CNZR
Manufacturer:
CIRRUSLOGICINC
Quantity:
20 000
Preliminary Product Information
Digital Amplifier Features
HP Detect/Mute
I²C or Hardware
Clocks & Data
Clocks & Data
System Clock
Crystal Driver
Configuration
Serial Audio
Serial Audio
Serial Audio
Fully Integrated Power MOSFETs
No Heatsink Required
> 100 dB Dynamic Range
< 0.1% THD+N @ 1 W
Configurable Outputs (10% THD+N)
Built-In Protection with Error Reporting
PWM Popguard
Click-Free Start-Up
Programmable Channel Delay for System
Noise & Radiated Emissions Management
http://www.cirrus.com
Analog In
Data I/O
Interrupt
Stereo
Reset
Programmable Power Foldback on
Thermal Warning
High Efficiency
1 x 30 W into 4 Ω, Parallel Full-Bridge
2 x 15 W into 8 Ω, Full-Bridge
2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W
into 8 Ω, Full-Bridge
Overcurrent/Undervoltage/Thermal
Overload Shutdown
Thermal Warning Reporting
I/O
30 W Digital Audio Amplifier with Integrated ADC
®
Crystal Oscillator Driver
Serial Audio Input Port
for Half-Bridge Mode
Auxiliary Serial Port
Register /Hardware
Multi-bit ΔΣ ADC
Delay Interface
Configuration
Serial Audio
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2007
2.5 V to 5 V
Thermal Warning
Thermal Feedback
(All Rights Reserved)
Error Protection
Parametric EQ
High-Pass
Bass/Treble
Adaptive
Loudness
Compensation
2-Ch Mixer
2.1 Bass Mgr
Linkwitz-Riley
Crossover
De-Emphasis
Volume
Processing
Audio
ADC Features
System Features
(Features continued on
Over Current
Under Voltage
Stereo, 24-bit, 48 kHz Conversion
Multi-bit Architecture
95 dB Dynamic Range (A-wtd)
-86 dB THD+N
Supports 2 Vrms Input with Passive
Components
Asynchronous 2-Channel Digital Serial Port
32 kHz to 96 kHz Input Sample Rates
Operation with On-Chip Oscillator Driver or
Applied SYS_CLK at 18.432, 24.576 or
27.000 MHz
Integrated Sample Rate Converter (SRC)
Spread Spectrum PWM Modulation
Low Quiescent Current
Eliminates Clock-Jitter Effects
Input Sample Rate Independent Operation
Simplifies System Integration
Reduces EMI Radiated Energy
Sample Rate
Multi-bit ΔΣ
Modulator
Integrated
Converter
PWM
with
Drive
Drive
Drive
Drive
Gate
Gate
Gate
Gate
8 V to 18 V
page
CS4525
VP
NOVEMBER '07
PGND
2)
PWM Modulator
PWM Modulator
Amplifier
Amplifier
Amplifier
Amplifier
DS726PP2
Out 1
Out 2
Out 3
Out 4
Output 1
Output 2

Related parts for CS4525-CNZ

CS4525-CNZ Summary of contents

Page 1

... Error Protection Over Current Thermal Warning Under Voltage Thermal Feedback This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS4525 page Gate Amplifier Out 1 Drive ...

Page 2

... The CS4525 automatically uses the on-chip oscillator driver in the absence of an applied master clock. The CS4525 is available in a 48-pin QFN package in Commercial grade (-10° to +70° C). The CRD4525-Q1 4-layer, 1 oz. copper and CRD4525-D1 2-layer, 1 oz. ...

Page 3

... PWM Modulator Configuration .............................................................................................. 50 6.1.9.1 PWM Channel Delay ................................................................................................ 50 6.1.9.2 PWM AM Frequency Shift ........................................................................................ 51 6.1.10 Headphone Detection & Hardware Mute Input ................................................................... 51 6.1.11 Interrupt Reporting .............................................................................................................. 53 6.1.12 Automatic Power Stage Shut-Down ................................................................................... 53 6.2 Hardware Mode ............................................................................................................................. 54 6.2.1 System Clocking ................................................................................................................... 54 6.2.2 Power-Up and Power-Down ................................................................................................. 54 6.2.2.1 Recommended Power-Up Sequence ....................................................................... 54 DS726PP2 CS4525 3 ...

Page 4

... PWM Signals Output Data Select (PWMDSel[1:0]) .............................................................. 73 9.4.3 Channel Delay Settings (OutputDly[3:0]) .............................................................................. 73 9.5 Foldback and Ramp Configuration (Address 05h) ......................................................................... 74 9.5.1 Select VP Level (SelectVP) .................................................................................................. 74 9.5.2 Enable Thermal Foldback (EnTherm) ................................................................................... 74 9.5.3 Lock Foldback Adjust (LockAdj) ........................................................................................... 74 9.5.4 Foldback Attack Delay (AttackDly[1:0]) ................................................................................ 75 9.5.5 Enable Foldback Floor (EnFloor) .......................................................................................... 75 4 CS4525 DS726PP2 ...

Page 5

... Peak Signal Limit All Channels (LimitAll) ............................................................................ 86 9.16.4 Peak Detect and Limiter Enable (EnLimiter) ....................................................................... 86 9.17 Limiter Configuration 2 (Address 5Dh) ......................................................................................... 87 9.17.1 Limiter Release Rate (RRate[5:0]) ...................................................................................... 87 9.18 Limiter Configuration 3 (Address 5Eh) ......................................................................................... 87 9.18.1 Enable Thermal Limiter (EnThLim) ..................................................................................... 87 9.18.2 Limiter Attack Rate (ARate[5:0]) ......................................................................................... 87 9.19 Power Control (Address 5Fh) ...................................................................................................... 88 DS726PP2 CS4525 5 ...

Page 6

... Figure 8.AUX Serial Port Interface Master Mode Timing .......................................................................... 22 Figure 9.SYS_CLK Timing from Reset ..................................................................................................... 23 Figure 10.PWM_SIGX Timing ................................................................................................................... 23 Figure 11.Control Port Timing - I²C ........................................................................................................... 24 Figure 12.Typical SYS_CLK Input Clocking Configuration ....................................................................... 26 Figure 13.Typical Crystal Oscillator Clocking Configuration ..................................................................... 27 Figure 14.Digital Signal Flow .................................................................................................................... 29 Figure 15.De-Emphasis Filter ................................................................................................................... 31 Figure 16.Bi-Quad Filter Architecture ........................................................................................................ 33 6 CS4525 DS726PP2 ...

Page 7

... Table 15. Serial Audio Interface Format Selection .................................................................................... 55 Table 16. Thermal Foldback Enable Selection ......................................................................................... 57 Table 17. PWM Output Switching Rates and Quantization Levels ........................................................... 58 Table 18. Low-Pass Filter Components - Half-Bridge ............................................................................... 59 Table 19. DC-Blocking Capacitors Values - Half-Bridge ........................................................................... 59 Table 20. Low-Pass Filter Components - Full-Bridge ............................................................................... 60 Table 21. Power Supply Configuration and Settings ................................................................................. 63 DS726PP2 Input Filter ........................................................................................... 61 RMS CS4525 7 ...

Page 8

... Reset (Input) - The device enters a low power mode and all internal registers are reset to their RST 8 default settings when this pin is driven low Thermal Pad Top-Down (Through Package) View 48-Pin QFN Package Pin Description CS4525 OUT1 35 PGND 34 PGND 33 OUT2 OUT3 29 PGND 28 PGND 27 OUT4 ...

Page 9

... XTO 47 Crystal Oscillator Output (Output) - Crystal oscillator driver output. XTI 48 Crystal Oscillator Input (Input) - Crystal oscillator driver input. Thermal Pad - Thermal relief pad for optimized heat dissipation. See Thermal Pad - page 65 for more information. DS726PP2 CS4525 “QFN Thermal Pad” ...

Page 10

... Reset (Input) - The device enters a low power mode and all internal registers are reset to their RST 8 default settings when this pin is driven low Thermal Pad Top-Down (Through Package) View 48-Pin QFN Package Pin Description CS4525 OUT1 35 PGND 34 PGND 33 OUT2 OUT3 29 PGND 28 PGND 27 OUT4 ...

Page 11

... Test Input (Input) - This pin is an input used for the crystal oscillator driver available only in soft- TSTI 48 ware mode. It must be tied to digital ground for normal hardware mode operation. Thermal Pad - Thermal relief pad for optimized heat dissipation. See Thermal Pad - page 65 for more information. DS726PP2 CS4525 “QFN Thermal Pad” ...

Page 12

... V-18.0 V Power MOSFET Output 8.0 V-18.0 V Power MOSFET Output 8.0 V-18.0 V Power MOSFET Output 8.0 V-18.0 V Power MOSFET Table 1. I/O Power Rails CS4525 Receiver 2.5 V-5.0 V, with Hysteresis 2.5 V-5.0 V, with Hysteresis 2.5 V-5.0 V 2.5 V-5 2.5 V-5.0 V 2.5 V-5.0 V ...

Page 13

... SDIN HP_DETECT/MUTE 7 43 AUX_SDOUT AUX_LRCK/AD0 45 AUX_SCLK 44 DLY_SDOUT 41 DLY_SDIN 42 VD_REG 11 SCL 2 SDA 3 INT 1 RST CS4525 + +18 V 0.1 µF 0.1 µF 470 µF 36 RAMP_CAP 35 OUT1 35 Output Filter OUT2 32 OUT3 29 Output Filter OUT4 26 Line PWM_SIG1 40 Output - or - Headphone PWM_SIG2 39 Output LVD VD or GND 9 16.2 kΩ ...

Page 14

... SYS_CLK CLK_FREQ0 1 CLK_FREQ1 2 TWR 41 ERRUVTE 42 43 ERROC EN_TFB 44 I²S/ ADC/SP 7 MUTE RST 8 TSTO 47 TSTI 48 VD_REG CS4525 + +18 V 0.1 µF 0.1 µF 470 µ RAMP_CAP 35 OUT1 35 Output Filter OUT2 32 OUT3 29 Output Filter OUT4 26 TSTO 40 TSTO 39 LVD 9 16.2 kΩ OCREF 21 FILT+ 15 VA_REG 13 0.1 µ ...

Page 15

... Speaker Delay Port Aux Gate Drive Out Subwoofer SYS_CLK Gate Drive Power Foldback HP/ PWM_SIG1 Line PWM_SIG2 Out Monitor Out Var/Fixed Out CS4525 Analog In Gate Drive Digital In Left Control Speaker Port Gate Drive Delay Port Aux Gate Out Drive Right SYS_CLK Speaker ...

Page 16

... Analog In Control Port Audio Delay 18.432 MHz Crystal In Clock Out Crystal Out Analog Out Figure 5. Typical System Configuration 3 CS4525 Monitor Out Var/Fixed Out CS4525 Analog In Gate Drive Digital In Control Port Gate Drive Delay Left Port Speaker Aux Gate Drive Out SYS_CLK ...

Page 17

... Gate Drive Out Left SYS_CLK Woofer Gate Drive Power Foldback PWM_SIG1 Sub PWM_SIG2 Out CS4525 Analog In Gate Drive Digital In Right Control Tweeter Port Gate Drive Delay Port Aux Gate Out Drive Right SYS_CLK Woofer Gate Power Drive Foldback PWM_SIG1 PWM_SIG2 CS4525 17 ...

Page 18

... VD 3.135 VD VP Commercial Symbol VP No Output Switching VP VD (Note (Note 3) V INA (Note 3) V IND Commercial stg CS4525 Min Nom Max Units 2.5 2.625 V 3.3 3.465 V 4.75 5.0 5.25 V 8.0 - 18.0 V °C -10 - +70 °C -10 - +125 section 6.7 on page 63 for Min ...

Page 19

... MHz XTAL/SYS_CLK equal to the applied clock divided by 384. DS726PP2 Min A-weighted 90 unweighted - - 2.5V (Note 5) 0.786* 3.3V 0.590* 5.0V 0.398*VD (Note -0.1 dB corner (Note 7) -3.0 dB -0.13 dB CS4525 Typ Max -86 -77 -72 - -32 - 0.05 - ±100 - ppm/° 0.827*VD 0.868*VD 0.621*VD 0.652*VD 0.419*VD 0.440* section 6.7 on page 63 ...

Page 20

... 50°C DS(ON Load min t Resistive Load r t Resistive Load 25°C, OCREF = 16.2 kΩ 25°C, OCREF = 18 kΩ 25°C, OCREF = 22 kΩ 25°C UVFALL 25°C UVRISE A CS4525 Figure 1 on page 13; PWM Switch Min Typ Max Units - 102 ...

Page 21

... XTI/XTO pins or the input SYS_CLK signal. CLK 9. is the number of bits per sample of the serial digital input. N bits 10. After powering up the CS4525, RST should be held low until the power supplies and clocks are stable. LRCK SCLK SDIN DS726PP2 = 25° 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD. ...

Page 22

... ClkFreq[1:0] = ‘01’ F SCLKO ClkFreq[1:0] = ‘10’ kHz S-In (Note 13) (Note 12, 13 kHz S-In T SCLKI 2 kHz SCLKI S-In t LTSF t SRDV t DIS t DIH = 1 SCLKI t LTSF LSB MSB t DISU LSB MSB CS4525 = 15 pF; Inputs: L Min Typ Max - F /384 - CLK - F /512 - CLK - F /512 - CLK - ...

Page 23

... Figure 9. SYS_CLK Timing from Reset = 25° 3.3 V; Load = 10 pF. Symbol Figure 10. PWM_SIGX Timing CS4525 Min Typ Max 18.432 18.617 24.576 24.822 27.000 27.270 Min Typ Max 18.432 18.617 24.576 24.822 27.000 27.270 - 1024*t ...

Page 24

... Repeated Start t high t hdst sud t sust low hdd Figure 11. Control Port Timing - I²C CS4525 L Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL. fc Stop Start ...

Page 25

... Low-Level PWM_SIGx Output Voltage Notes: 21. Digital interface signals include all pins sourced from the VD supply as shown in Characteristics” on page DS726PP2 3.3 V (Note 19) 1 kHz 60 Hz Symbol (Note 21 OHPS OLPS 12. CS4525 Min Typ Max Units - 180 - mW - 2.8 - 2.25 2.5 2. 2.25 2.5 2. 0.5*VA_REG - - VA_REG - - ...

Page 26

... WARNING: The system clock source must never be removed or stopped while any of the power output stages are powered-up (the PDnAll bit and any of the PDnOut1, PDnOut2, or PDnOut3/4 bits are cleared) and connected to a load. Doing so may result in permanent damage to the CS4525 and connected trans- ducers. ...

Page 27

... Also, the DivSysClk bit allows the frequency of the generated internal clock to be divided by 2 prior to be- ing driven out of the SYS_CLK. It should be noted that the internal oscillator driver is disabled when the CS4525 is in reset (RST is low). Any external devices connected to the SYS_CLK output will not receive a clock signal until the CS4525 is taken out of reset ...

Page 28

... Power-Up and Power-Down The CS4525 will remain in a completely powered-down state with the control port inaccessible until the RST pin is brought high. Once RST is high, the control port will be accessible, but all other internal blocks will remain powered-down until they are powered-up via the control port or until hardware mode is en- tered ...

Page 29

... The serial audio input port digital interface format is configured by the DIF[2:0] bits in the Input Config reg- ister. The CS4525 internal ADC includes a dedicated high-pass filter to remove any DC content from the ADC output signal prior to the internal ADC/serial audio input port input multiplexor. This high-pass filter can be bypassed by clearing the EnAnHPF bit ...

Page 30

... Digital Signal Processing High-Pass Filter The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove any DC content from the input signal prior to the remaining internal digital signal processing blocks. The high-pass filter operates by continuously subtracting a measure of the DC offset from the input signal and may be used regardless of the input data source ...

Page 31

... De-Emphasis The CS4525 includes an on-chip digital de-emphasis filter optimized for a sample rate of 44.1 kHz to ac- commodate audio recordings that utilize 50/15 μs pre-emphasis equalization as a means of noise reduc- tion. The filter response is shown in DeEmph bit in the Tone Config register. Nominal Sample Rate 32 kHz, 44 ...

Page 32

... Gain Level (Bass[3:0])” on page 78 32 Treble Fc 0 Treble Fc 1 5.0 kHz 7.0 kHz 4.8 kHz 6.7 kHz 5.2 kHz 7.3 kHz Table 3. Treble Shelving Filter Corner Frequencies CS4525 Treble Fc 2 Treble Fc 3 10.0 kHz 15.0 kHz 9.6 kHz 14.4 kHz 10.4 kHz 15.6 kHz DS726PP2 ...

Page 33

... Parametric EQ The CS4525 implements 5 fully programmable parametric EQ filters. The filters are implemented in the bi-quad form shown below. x[n] This architecture is represented by the equation shown below where y[n] represents the output sample value and x[n] represents the input sample value. y[ The coefficients are represented in binary form by 24-bit signed values stored in 3.21 two’s complement format. The 3 MSB’ ...

Page 34

... Adaptive Loudness Compensation The CS4525 includes adaptive loudness compensation to enhance the audibility of program material at low volume levels. The adaptive loudness compensation feature operates by varying the bass and treble boost of the tone control shelving filters as the volume level changes. The level of boost added to the shelving filters is determined by the average of the effective volume set- tings of channels A and B after the master volume control ...

Page 35

... The CS4525 automatically detects the input sample rate and chooses the appropriate filter set to apply. The available bass management cross-over frequencies are shown in figured with the BassMgr[2:0] bits in the EQ Config register ...

Page 36

... By default, master vol- ume is set to +3dB; if the CS4525 is being used to control the application’s master volume, then it is recommended to change this value to a comfortable listening level before enabling the PWM powered out- puts ...

Page 37

... This default functionality is designed to keep all output channels at the same volume level while the limiter is in use. This behavior can be disabled by clearing the LimitAll bit in the Limiter Cfg 1 register. DS726PP2 Attack/Release Sound Cushion Attack/Release Sound Cushion Min[2:0] ARate[5:0] Figure 17. Peak Signal Detection & Limiting CS4525 RRate[5:0] 37 ...

Page 38

... The limiter can be enabled by setting the EnLimiter bit in the Limiter Cfg 1 register The limiter can also be used in conjunction with the thermal limiter function to provide thermal error pro- tection to the CS4525. The thermal limiter function is described in Referenced Control Register Location EnLimiter ............................. “ ...

Page 39

... In this state, the peak signal limiter’s operation will follow the EnLimiter, Min[2:0], and Max[2:0] bits with no internal modification. If EnThLim is set again before the CS4525 has been reset (by toggling the RST pin low and then high), thermal limiting will engage immediately. ...

Page 40

... Thermal Foldback The CS4525 implements comprehensive thermal foldback features to guard against damaging thermal overload conditions. Thermal foldback is similar to the thermal limiting described on features attenuate the output signal in response to thermal warnings conditions; however, thermal fold- back will attenuate as a function of how long thermal warning has been active whereas thermal limiter always limits by a constant amount ...

Page 41

... Thermal warnings will only affect the foldback algorithm and cause attenuation to be applied when en- abled by the EnTherm bit in the Foldback Cfg register. The CS4525 can be configured to accept an external thermal warning indicator input. When in this con- figuration, an active input signal indicates that a thermal warning threshold has been exceeded. If thermal foldback is enabled, the foldback algorithm will respond as described above making no distinction be- tween an internal or external thermal warning condition ...

Page 42

... A and Channel B Low-Pass Sensitivity Adjust (LowPass[3:0])” on page 81 42 Input Sample Rate 32 kHz 44.1 kHz 3.0 kHz 2.88 kHz 3.2 kHz 3.07 kHz 3.4 kHz 3.26 kHz Table 5. 2-Way Cross-Over Frequencies CS4525 48 kHz, 96 kHz 3.13 kHz 3.34 kHz 3.55 kHz DS726PP2 ...

Page 43

... Auxiliary Serial Output The CS4525 includes a stereo auxiliary serial output which allows an external device to leverage on its internal signal processing and routing capabilities. The auxiliary serial output can receive its data from any of the sources shown in the The supported output data routing configurations are shown in is configured to output channels A and B on the auxiliary output data left and right channels respectively ...

Page 44

... The port routes the serial data from the selected input source (the ADC or the serial input port) out to an external serial audio delay device, and then back in to the CS4525 internal dig- ital sound processing blocks. The delay serial audio interface signals include DLY_SDOUT and DLY_SDIN/EX_TWR and are clocked from AUX_LRCK and AUX_SCLK. The serial data is output on the DLY_SDOUT pin and input on the DLY_SDIN/EX_TWR in the format specified by the AuxI² ...

Page 45

... Down (PDnAll)” on page 89 6.1.7.2 PWM Popguard Transient Control The CS4525 uses Popguard technology to minimize the effects of power-up and power-down output tran- sients commonly produced by half-bridge, single supply amplifiers implemented with external DC-block- ing capacitors connected in series with the audio outputs. ...

Page 46

... PWM amplifier such as the CS4412 analog input to a headphone amplifier or a line-out amplifier. To eliminate power-up pops when used to supply an external PWM amplifier, the CS4525 implements the same click-free start-up function on the PWM_SIG outputs as it does for its own powered PWM outputs. ...

Page 47

... Engage the reset/power-down feature of the external PWM amplifier. 3. Set the PDnAll bit in the Power Ctrl register to disable the PWM modulators and set the PWM_SIG outputs to a drive a logic ‘0’. 4. Power down the remainder of the system (if applicable). DS726PP2 section on page 51. CS4525 Headphone 47 ...

Page 48

... Power down the remainder of the system (if applicable). Referenced Control Register Location PDnAll ................................. “Power Down (PDnAll)” on page 89 HiZPSig ............................... “Hi-Z PWM_SIG Outputs (HiZPSig)” on page 79 PWMDSel[1:0]..................... “PWM Signals Output Data Select (PWMDSel[1:0])” on page 73 Master Volume .................... “Master Volume Control (MVol[7:0])” on page 82 48 section on page 51. CS4525 Headphone DS726PP2 ...

Page 49

... Pin Mode (HP/Mute)” on page 70 BassMgr[2:0] ....................... “Bass Cross-Over Frequency (BassMgr[2:0])” on page 79 DS726PP2 PWM_SIG1 Disabled. Channel 1 Channel 1 Channel 2 Table 10. PWM Logic-Level Output Configurations section and Figure 14 on page 29. CS4525 PWM_SIG2 Disabled. Channel 2 Sub Channel Sub Channel section on page 51 for more informa- 49 ...

Page 50

... PWM switching frequency can be easily modified to eliminate interference with AM tuners. 6.1.9.1 PWM Channel Delay The CS4525 includes a PWM output signal delay mechanism. This mechanism allows the PWM switching edges to be offset between channels as a method of managing switching noise and reducing radiated emissions. ...

Page 51

... PWM AM Frequency Shift When using a PWM amplifier in a system containing an AM tuner possible that the PWM switch rate conflicts with the desired tuning frequency of the AM tuner. To overcome this effect, the CS4525 includes a PWM switch rate shift feature. The feature adjusts the PWM switching frequency and quantization levels to remove interference when the desired tuning frequency tuner is positioned near a harmonic of the PWM switching rate ...

Page 52

... X 01, 10 01, 10 000 10 (Disabled) 11 001 through 111 01, 10 Table 12. Output of PWM_SIG Outputs CS4525 PWM_SIG1 PWM_SIG2 Output Output High Impedance High Impedance Driven Low Driven Low Channel 1 Channel 2 Channel 1 Mute Channel 2 Mute Channel 1 Channel 2 Channel 1 Sub Channel Channel 2 ...

Page 53

... With the AutoRetry function enabled, the CS4525 will place the PWM power outputs in a high-impedance state upon the sensing of an over-current condition, wait approximately 85 ms, and then re-engage the power outputs in an attempt to resume normal operation ...

Page 54

... Hardware Mode A limited feature set is available when the CS4525 powers up in hardware mode. The available features are described in the following sections. All device configuration is achieved via hardware control input pins. 6.2.1 System Clocking In hardware mode, the CS4525 must be clocked by a stable external clock source input on the SYS_CLK pin ...

Page 55

... Low High 6.2.4 PWM Channel Delay In hardware mode, the CS4525 offsets the PWM switching edges between channels as a method of man- aging switching noise and reducing radiated emissions. The OUT3/OUT4 signal pair is delayed from the OUT1/OUT2 signal pair by 4 SYS_CLK cycles as shown in Figure 23 below ...

Page 56

... It should be noted that the auto-mute, soft-ramp, and zero-crossing detection features are active in hard- ware mode. 6.2.5.3 Warning and Error Reporting The CS4525 is capable of reporting various error and warning conditions on its TWR, ERROC, and ER- RUVTE pins. • The TWR pin indicates the presence of a thermal warning condition. When active concurrently with the ERRUVTE pin, indicates a thermal error condition. • ...

Page 57

... Thermal Foldback In hardware mode, the CS4525 implements a thermal foldback feature to guard against damaging thermal overload conditions. The thermal foldback feature begins limiting the volume of the digital audio input to the amplifier stage as the junction temperatures rise above the maximum safe operating range specified ...

Page 58

... To easily accommodate input sample rates ranging from 32 kHz to 96 kHz without requiring the adjustment of output filter component values, the CS4525 utilizes a sample rate converter (SRC) to keep the PWM switching frequency fixed regardless of the input sample rate. The SRC operates by upsampling the variable input sample rate to a fixed output switching rate, typically 384 kHz for most audio applications ...

Page 59

... Table 19 shows the component values for C2 based on corner frequency Load Corner Frequency 4 Ω 120 Hz 6 Ω 120 Hz 8 Ω 110 Hz CS4525 Table 18 shows the component values C1 1.0 µF 0.68 µF 0.47 µF C2 1000 µF 680 µF 330 µF 680 µF 390 µF 220 µ ...

Page 60

... VP L1 680 pF *Diode is Rohm RB160M-30 or 5.6 Ω equivalent VP L2 680 pF 5.6 Ω Figure 27. Output Filter - Full-Bridge Load L1 Ω 10 µH 6 Ω 15 µH 8 Ω 22 µH Table 20. Low-Pass Filter Components - Full-Bridge CS4525 Table 20 shows the component C1 C1 1.0 µF 0.47 µF 0.47 µF DS726PP2 ...

Page 61

... Left Input Right Input It should be noted that the external DC blocking capacitor forms a high-pass filter with the CS4525’s input impedance. Both filters shown above have less than 0.2 dB attenuation due to this effect. Increas- ing the value of this capacitor will lower this high-pass corner frequency, and decreasing it’s value will in- crease the corner frequency ...

Page 62

... Serial Audio Interfaces The CS4525 interfaces to external digital audio devices via the serial audio input port and the auxiliary/delay serial ports. The serial audio input port provides support for I²S, Left-Justified and Right-Justified data formats and op- erates in slave mode only, with LRCK and SCLK as inputs. The input LRCK signal must be equal to the sample rate, Fs and must be synchronous to the serial bit clock, SCLK, which is used to sample the data bits ...

Page 63

... Integrated VD Regulator The CS4525 includes two internal linear regulators, one from the VD supply voltage to provide a fixed supply to its internal digital blocks, and another from the VD supply voltage to provide a fixed to its internal analog blocks. The LVD pin must be set to indicate the voltage present on the VD pin as shown ...

Page 64

... SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4525 after a Start condition consists bit device address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101 ...

Page 65

... QFN Thermal Pad The CS4525 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers ...

Page 66

... Reserved SPRate1 SPRate0 AuxI²S/LJ RChDSel1 LockAdj AttackDly1 AttackDly0 PreScale0 Reserved RChMix1 EnDigHPF TrebFc1 TrebFc0 Treble1 Treble0 Bass3 BassMgr2 BassMgr1 BassMgr0 CS4525 HP/Mute PhaseShift FreqShift DIF2 DIF1 RChDSel0 LChDSel1 LChDSel0 EnFloor RmpSpd1 RmpSpd0 RChMix0 LChMix1 LChMix0 BassFc1 BassFc0 EnToneCtrl Bass2 Bass1 ...

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... MSB ............................................................................................................................. BiQuad 5 50h MSB-8 ............................................................................................................................. B1 Coeff 51h LSB+7 ............................................................................................................................. 52h MSB ............................................................................................................................. BiQuad 5 53h MSB-8 ............................................................................................................................. B2 Coeff 54h LSB+7 ............................................................................................................................. DS726PP2 CS4525 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 LSB+8 MSB-7 ...

Page 68

... RRate4 RRate3 ARate5 ARate4 ARate3 SelectVD PDnADC PDnOut3 ChOvfl AmpErr SRCLockM ADCOvflM SubOvflSt Ch2OvflSt Ch1OvflSt OverCurr2 OverCurr1 ExtAmpSt DeviceID2 DeviceID1 DeviceID0 CS4525 2WayFreq2 2WayFreq1 2WayFreq0 HighPass2 HighPass1 HighPass0 MVol2 MVol1 ChAVol2 ChAVol1 ChBVol2 ChBVol1 SubVol2 SubVol1 MuteSub MuteChB MuteChA Min1 Min0 ...

Page 69

... ClkFreq[1:0] Setting Specified Nominal Input Clock Frequency 00 ........................................18.432 MHz 01 ........................................24.576 MHz 10 ........................................27.000 MHz 11.........................................Reserved DS726PP2 ClkFreq0 HP/MutePol = F SYS_CLK XTAL = F /2 SYS_CLK XTAL XTI Switching Specifications table on page 23 for complete input frequency range specifications. CS4525 HP/Mute PhaseShift FreqShift table on page 23 and the 69 ...

Page 70

... AM Frequency Shifting (FreqShift) Default = 0 Function: Controls the state of the PWM AM frequency shift feature. See for more information. FreqShift Setting AM Frequency Shift State 0 .......................................... Frequency shift disabled. 1 .......................................... Frequency shift enabled. 70 CS4525 “Headphone Detection & Hardware Mute “PWM AM Frequency Shift” on page 51 DS726PP2 ...

Page 71

... DS726PP2 SPRate1 SPRate0 “Serial Audio Interfaces” on page CS4525 2 1 DIF2 DIF1 62. 0 DIF0 71 ...

Page 72

... RChDSel[1:0] Setting Aux Serial Port Right Channel Output Data Source 00 ........................................ Channel A. 01 ........................................ Channel B. 10 ........................................ Sub Channel. 11......................................... Channel B crossover high-pass output AuxI²S/LJ RChDSel1 “Serial Audio Delay & Warning Input Port” on “Serial Audio Interfaces” on page CS4525 RChDSel0 LChDSel1 LChDSel0 62. DS726PP2 ...

Page 73

... SYS_CLK or crystal input clock source. These bits can DS726PP2 PWMDSel0 OutputDly3 “Output Channel Configurations” on page 45 for more information. PWM_SIG2 output disabled. Channel 2 output on PWM_SIG2. Sub Channel output on PWM_SIG2. Sub Channel output on PWM_SIG2. CS4525 OutputDly2 OutputDly1 OutputDly0 for more informa- “PWM_SIG Logic- 73 ...

Page 74

... Controls the operation of the foldback lock adjustment feature. See more information. LockAdj Setting Foldback Adjustment Lock State 0 .......................................... Attenuation lock disabled. 1 .......................................... Attenuation lock enabled AttackDly1 AttackDly0 “Thermal Foldback” on page 40 CS4525 “PWM Channel Delay” EnFloor RmpSpeed1 RmpSpeed0 for more information. “Thermal Foldback” on page 40 DS726PP2 for ...

Page 75

... DS726PP2 “Thermal Foldback” on page 40 “Thermal Foldback” on page 40 “PWM Popguard Transient Control” on page Reserved RChMix1 “Pre-Scaler” on page 30 CS4525 for more information. for more information. for more in RChMix0 LChMix1 LChMix0 for more information. 75 ...

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... Loudness Setting Adaptive Loudness Compensation State 0 .......................................... Disabled. 1 .......................................... Enabled. 76 “Channel Mixer” on page 30 “Channel Mixer” on page TrebFc1 TrebFc0 CS4525 for more information. for more information BassFc1 BassFc0 EnToneCtrl “De-Emphasis” on page 31 for more infor- “Adaptive Loudness Compen- DS726PP2 0 ...

Page 77

... When set, enables the bass and treble shelving filters. When cleared, disables the bass and treble shelv- ing filters. EnToneCtrl Setting Tone Control Filter State 0 ..........................................Bass and treble shelving filters disabled. 1 ..........................................Bass and treble shelving filters enabled. DS726PP2 for more information. CS4525 “Digital Signal Processing 77 ...

Page 78

... To make multiple changes in these control port registers take effect simultaneously, enable the Freeze bit, make all register changes, then disable the Freeze bit. Freeze Setting Register Freeze State 0 .......................................... Register freeze disabled. 1 .......................................... Register freeze enabled Treble0 Bass3 BassMgr1 BassMgr0 CS4525 Bass2 Bass1 Bass0 Reserved EnChBPEq EnChAPEq DS726PP2 ...

Page 79

... Function: Enables the parametric EQ bi-quad filters for channel B. EnChBPEq Setting Channel B Parametric EQ State 0 ..........................................Disabled. 1 ..........................................Enabled. 9.9.5 Enable Channel A Parametric EQ (EnChAPEq) Default = 0 Function: Enables the parametric EQ bi-quad filters for channel A. EnChAPEq Setting Channel A Parametric EQ State 0 ..........................................Disabled. 1 ..........................................Enabled. DS726PP2 CS4525 “Bass Management” ...

Page 80

... Auto-Mute (AutoMute) Default = 1 Function: When enabled, the outputs of the CS4525 will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. See tion. ...

Page 81

... Controls the 2-way cross-over low-pass sensitivity adjustment. See trol” on page 41 for more information. LowPass[3:0] Setting Sensitivity Compensation Level 0000 ....................................0.0 dB 0001 ....................................-0.5 dB 0010 ....................................-1.0 dB ..................................... 1000 ....................................-4.0 dB ..................................... 1110 .....................................-7.0 dB 1111 .....................................-7.5 dB DS726PP2 LowPass0 HighPass3 CS4525 HighPass2 HighPass1 HighPass0 “2-Way Crossover & Sensitivity Con- 81 ...

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... Master Volume Setting 0000 0000 ........................... +24 dB ............................ 0010 1010 ........................... +3 dB ............................ 0011 0000............................ 0.0 dB 0011 0001............................ -0.5 dB 0011 0010............................ -1.0 dB ............................ 1111 1110............................. -103.0 dB 1111 1111 ............................. Master Mute MVol4 MVol3 CS4525 “2-Way Crossover & Sensitivity Con MVol2 MVol1 MVol0 “Volume and Muting Control” on DS726PP2 ...

Page 83

... Mute DS726PP2 ChXVol4 ChXVol3 SubVol4 SubVol3 “Volume and Muting Control” on page 36 CS4525 ChXVol2 ChXVol1 ChXVol0 “Volume and Muting Control” SubVol2 SubVol1 SubVol0 for more 83 ...

Page 84

... Independent Channel A & B Mute (MuteChX) Default = 0 Function: The respective channel’s power PWM, logic-level PWM, and auxiliary serial data outputs will enter a mute state when enabled. The delay serial output will be unaffected if the delay port is enabled. The muting InvCh1 MuteADC CS4525 MuteSub MuteChB MuteChA DS726PP2 ...

Page 85

... Sets a minimum level below full scale at which the limiter will begin to release its applied attenuation. Min[2:0] Setting Minimum Threshold Setting 000 ......................................0.0 dB 001 ......................................-3.0 dB 010 ......................................-6.0 dB 011.......................................-9.0 dB 100 ......................................-12.0 dB 101 ......................................-18.0 dB 110.......................................-24.0 dB 111 .......................................-30.0 dB DS726PP2 for more information. “Volume and Muting Control” on page Min2 Min1 CS4525 for more information Min0 LimitAll EnLimiter 85 ...

Page 86

... Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak signal limit- ing is performed by digital attenuation. EnLimiter Setting Peak Signal Limiter State 0 .......................................... Peak signal limiter disabled. 1 .......................................... Peak signal limiter enabled. 86 “Peak Signal Limiter” on page 37 for more information. CS4525 DS726PP2 ...

Page 87

... The limiter attack rate is a function of the sampling frequency, Fs, and the soft and zero cross setting. ARate[5:0] Setting Limiter Attack Rate 00000 ..................................Fastest attack. ................................... 11111....................................Slowest attack. DS726PP2 RRate4 RRate3 ARate4 ARate3 CS4525 RRate2 RRate1 RRate0 ARate2 ARate1 ARate0 “Thermal Limiter” section on 87 ...

Page 88

... Enables the PWM power output over-current protection feature described in Shut-Down” on page 53. WARNING: The EnOCProt bit must never to changed from its default value of 1. Doing so will disable the over-cur- rent protection feature and may result in permanent damage to the CS4525. 9.19.3 Select VD Level (SelectVD) Default = 1 Function: This bit selects between ...

Page 89

... Power Down (PDnAll) Default = 1 Function: The CS4525 will enter a power-down state when this function is enabled: 1. The power PWM outputs will be held in a high-impedance state. 2. The logic-level PWM outputs will continuously drive a logic ‘0’ if the HiZPSig bit is set and will be held in a high-impedance state if the HiZPSig bit is clear ...

Page 90

... ADC Overflow Interrupt (ADCOvfl) Function: This bit is read only. When set, indicates that an over-range condition occurred anywhere in the CS4525 ADC signal path and has been clipped to positive or negative full scale as appropriate since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register ...

Page 91

... ChOvfl condition is masked, meaning that its occurrence will not affect the INT pin. How- ever, the ChOvfl, ChXOvflSt, and SubOvflSt bits will continue to reflect the overflow state of the individual channels. ChOvflM Setting ChOvfl INT Pin Mask State 0 ..........................................ChOvfl condition masked. 1 ..........................................ChOvfl condition un-masked. DS726PP2 CS4525 91 ...

Page 92

... ADC Overflow (ADCOvflSt) Function: This bit is read only and will identify the presence of an overflow condition within the ADC. When set, in- dicates that an over-range condition is currently occurring in the CS4525 ADC signal path and has been clipped to positive or negative full scale. ADCOvflSt Setting ADC Overflow State 0 ...

Page 93

... This status bit reflects the active state of the external thermal warning input signal. ExtAmpSt Setting External Amplifier Status 0 ..........................................A thermal warning condition is not currently being reported by an external amplifier. 1 ..........................................A thermal warning condition is currently being reported by an external amplifier. DS726PP2 OverCurr1 ExtAmpErr CS4525 Reserved UVTE1 UVTE0 93 ...

Page 94

... Device I.D. and Revision (Address 63h) - Read Only 7 6 DeviceID4 DeviceID3 DeviceID2 9.23.1 Device Identification (DeviceID[4:0]) Default =11111 Function: Identification code for the CS4525. DeviceID[4:0] Setting Device ID Notes 11111.................................... Permanent device identification code. 9.23.2 Device Revision (RevID[2:0]) Function: Identifies the CS4525 device revision. RevID[2:0] Setting Device Revision 000 ...

Page 95

... Cirrus Logic, “AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,” Version 6.0, February 1998. 2. Cirrus Logic, “AN22: Overview of Digital Audio Interface Data Structures, Version 2.0”, February 1998.; A useful tutorial on digital audio specifications. 3. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com DS726PP2 CS4525 95 ...

Page 96

... Side View MAX MIN -- 0.0354 -- -- 0.0020 0.00 0.0157 0.30 0.2736 6.65 0.2736 6.65 0.0276 0.45 JEDEC #: MO-220 Controlling Dimension is Millimeters. Table 22: CS4525 Bottom View MILLIMETERS NOM MAX -- 0.90 -- 0.05 0.35 0.40 9.00 BSC 6.80 6.95 9.00 BSC 6.80 6.95 0.65 BSC ...

Page 97

... Board 2 Layer / 1oz. Copper CRD4525-D1 Reference Design Board DS726PP2 Symbol θ RMS Package Temp Range Container Pb-Free Grade 48-QFN Yes Commercial -10° to +70° CS4525 Min Typ Max - 1 - (assuming 85% efficiency) Order# Rail CS4525-CNZ Tape and CS4525-CNZR Reel - - CRD4525- CRD4525-D1 Units °C/Watt 97 ...

Page 98

... TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. 98 Changes CS4525 DS726PP2 ...

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