MT29F8G08AAAWP-ET:ATR Micron Technology Inc, MT29F8G08AAAWP-ET:ATR Datasheet - Page 24

• Manufacturer Part Number: MT29F8G08AAAWP-ET:ATR
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08AAAWP-ET:ATR

• Cell Type: NAND
• Density: 8Gb
• Access Time (max): 18ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

RANDOM DATA READ 05h-E0h
Figure 19:
PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh
PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
2gb_nand_m29b__2.fm - Rev. I 1/06 EN
R/B#
I/Ox
RE#
00h
RANDOM DATA READ Operation
(5 Cycles)
Address
30h
The RANDOM DATA READ command enables the user to specify a new column address
so the data at single or multiple addresses can be read. The random read mode is
enabled after a normal PAGE READ (00h-30h sequence).
Random data can be output after the initial page read by writing an 05h-E0h command
sequence along with the new column address (two cycles).
The RANDOM DATA READ command can be issued without limit within the page.
Only data on the current page can be read. Pulsing the RE# pin outputs data sequen-
tially. See Figure 19 on page 24.
Micron NAND Flash devices have a cache register that can be used to increase READ
operation speed when accessing sequential pages in a block.
First, a normal PAGE READ (00h-30h) command sequence is issued. (See Figure 20 on
page 25 for operation details.) The R/B# signal goes LOW for
to transfer the first page of data from the memory to the data register. After R/B# returns
to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the
command register. R/B# goes LOW for
the data register to the cache register. Once the data register contents are transferred to
the cache register, another PAGE READ is automatically started as part of the 31h com-
mand. Data is transferred from the next sequential page of the memory array to the data
register during the same time data is being read serially (pulsing of RE#) from the cache
register. If the total time to output data exceeds
The second and subsequent pages of data are transferred to the cache register by issuing
additional 31h commands. R/B# will stay LOW up to
depending on whether the previous memory-to-data-register transfer was completed
prior to issuing the next 31h command. If the data transfer from memory to the data reg-
ister is not completed before the 31h command is issued, R/B# stays LOW until the
transfer is complete.
It is not necessary to output a whole page of data before issuing another 31h command.
R/B# will stay LOW until the previous PAGE READ is complete and the data has been
transferred to the cache register.
To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh)
command is issued. This command transfers data from the data register to the cache
register without issuing another PAGE READ. (See Figure 20 on page 25.)
t
R
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
Data Output
24
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DCBSYR1 while data is being transferred from
05h
(2 Cycles)
Address
t
R, then the PAGE READ is hidden.
t
DCBSYR2. This time can vary,
E0h
Command Definitions
t
R during the time it takes
©2004 Micron Technology, Inc. All rights reserved.
Data Output