TDA8932BTW/N2,118

Manufacturer Part NumberTDA8932BTW/N2,118
DescriptionIC AMP AUDIO CLASS D 32HTSSOP
ManufacturerNXP Semiconductors
TypeClass D
TDA8932BTW/N2,118 datasheets
 

Specifications of TDA8932BTW/N2,118

Output Type1-Channel (Mono) or 2-Channel (Stereo)Package / Case32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
Max Output Power X Channels @ Load55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 OhmVoltage - Supply10 V ~ 36 V, ±5 V ~ 18 V
FeaturesDepop, Differential Inputs, Mute, Short-Circuit and Thermal ProtectionMounting TypeSurface Mount
ProductClass-DOutput Power55 W
Available Set Gain36 dBCommon Mode Rejection Ratio (min)75 dB
Thd Plus Noise0.007 %Operating Supply Voltage22 V
Supply Current0.145 mAMaximum Power Dissipation5000 mW
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
Audio Load Resistance8 OhmsDual Supply Voltage+/- 11 V
Input Signal TypeDifferentialMinimum Operating Temperature- 40 C
Output Signal TypeDifferential, SingleSupply TypeSingle or Dual
Supply Voltage (max)36 VSupply Voltage (min)10 V
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names935283479118
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UJA1079
LIN core system basis chip
Rev. 02 — 27 May 2010
1. General description
The UJA1079 core System Basis Chip (SBC) replaces the basic discrete components
commonly found in Electronic Control Units (ECU) with a Local Interconnect Network
(LIN) interface.
The UJA1079 supports the networking applications used to control power and sensor
peripherals by using the LIN interface as a local sub-bus.
The core SBC contains the following integrated devices:
LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with
LIN 1.3
Advanced independent watchdog (UJA1079/xx/WD versions)
250 mA voltage regulator for supplying a microcontroller; extendable with external
PNP transistor for increased current capability and dissipation distribution
Serial Peripheral Pnterface (SPI) (full duplex)
2 local wake-up input ports
Limp home output port
In addition to the advantages gained from integrating these common ECU functions in a
single package, the core SBC offers an intelligent combination of system-specific
functions such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Detailed status reporting on system and sub-system levels
The UJA1079 is designed to be used in combination with a microcontroller. The SBC
ensures that the microcontroller always starts up in a controlled manner.
Product data sheet

TDA8932BTW/N2,118 Summary of contents

  • Page 1

    UJA1079 LIN core system basis chip Rev. 02 — 27 May 2010 1. General description The UJA1079 core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a Local Interconnect Network (LIN) ...

  • Page 2

    ... NXP Semiconductors 2. Features and benefits 2.1 General Contains LIN ECU functions: LIN transceiver Scalable 3 voltage regulator delivering up to 250 mA for a microcontroller and peripheral circuitry; an external PNP transistor can be connected for better heat distribution over the PCB Watchdog with Window and Timeout modes and on-chip oscillator ...

  • Page 3

    ... NXP Semiconductors Window, Timeout (with optional cyclic wake-up) and Off modes supported (with automatic re-enable in the event of an interrupt) 16-bit Serial Peripheral Interface (SPI) for configuration, control and diagnosis Global enable output for controlling safety-critical hardware Limp home output (LIMP) for activating application-specific ‘limp home’ hardware in ...

  • Page 4

    ... NXP Semiconductors 4. Block diagram BAT GND SCK SDI SDO SCSN WAKE1 WAKE WAKE2 WDOFF EN DLIN LIN TXDL RXDL Fig 1. Block diagram UJA1079_2 Product data sheet SYSTEM CONTROLLER BAT BAT LIN All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 ...

  • Page 5

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol i.c. i.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCSN i.c. i.c. TEST1 WDOFF LIMP UJA1079_2 Product data sheet i. TXDL 4 V1 RXDL 5 RSTN 6 INTN SDI SDO 10 SCK ...

  • Page 6

    ... NXP Semiconductors Table 2. Symbol WAKE1 WAKE2 i.c. i.c. i.c. GND i.c. LIN DLIN i.c. WBIAS VEXCC TEST2 VEXCTRL BAT The exposed die pad at the bottom of the package allows for better heat dissipation from the SBC via the printed circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND ...

  • Page 7

    ... NXP Semiconductors The system controller is a state machine. The SBC operating modes, and how transitions between modes are triggered, are illustrated in more detail in the following sections. UJA1079_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 ...

  • Page 8

    ... NXP Semiconductors V below BAT power-off threshold V th(det)poff (from all modes) V below BAT power-on threshold V th(det)pon LIN: Active/Lowpower successful watchdog trigger Fig 3. UJA1079 system controller UJA1079_2 Product data sheet Overtemp V1: OFF limp home = LOW (active) LIN: Off and high resistance watchdog: OFF ...

  • Page 9

    ... NXP Semiconductors 6.1.2 Off mode The SBC switches to Off mode from all other modes if the battery supply drops below the power-off detection threshold (V and the bus system high-resistive state. As soon as the battery supply rises above the power-on detection threshold (V the SBC goes to Standby mode, and a system reset is executed (reset pulse width long or short ...

  • Page 10

    ... NXP Semiconductors 6.1.5 Sleep mode Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the Mode_Control register no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source is enabled (LIN or WAKE). Any attempt to enter Sleep mode while one of these conditions has not been satisfied will result in a short reset (3.6 ms minimum pulse width ...

  • Page 11

    ... NXP Semiconductors SCS SCK 01 sampled SDI X SDO X floating Fig 4. SPI timing protocol 6.2.2 Register map The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines the selected register as read/write or read only. Table 3. Address bits 15, 14 and 13 ...

  • Page 12

    ... NXP Semiconductors 6.2.3 WD_and_Status register Table 4. WD_and_Status register Bit Symbol Access Power-on default 15:13 A2, A1 000 WMC R/W 0 [1] 10:8 NWP R/W 100 7 WOS/SWR R V1S reserved WLS1 WLS2 R - 2:0 reserved R 000 [1] Bit NWP is set to it’s default value (100) after a reset. ...

  • Page 13

    ... NXP Semiconductors 6.2.4 Mode_Control register Table 5. Mode_Control register Bit Symbol Access Power-on default 15:13 A2, A1 001 12 RO R/W 0 11:10 MC R/W 00 [1] 9 LHWC R/W 1 [2] 8 LHC R ENC R LSC R WBC R PDC R/W 0 3:0 reserved R 0000 [1] Bit LHWC is set to 1 after a reset. [2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset. ...

  • Page 14

    ... NXP Semiconductors 6.2.5 Int_Control register Table 6. Int_Control register Bit Symbol Access Power-on default 15:13 A2, A1 010 V1UIE R reserved STBCL R reserved R 0 7:6 WIC1 R/W 00 5:4 WIC2 R reserved RTHC R WSE1 R/W 0 UJA1079_2 Product data sheet Description register address access status 0: register set to read/write ...

  • Page 15

    ... NXP Semiconductors Table 6. Int_Control register Bit Symbol Access Power-on default 0 WSE2 R/W 0 6.2.6 Int_Status register [1] Table 7. Int_Status register Bit Symbol Access Power-on default 15:13 A2, A1 011 V1UI R reserved LWI R reserved R WI1 R POSI R WI2 R/W 0 3:0 reserved R 0000 [1] An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register. ...

  • Page 16

    ... NXP Semiconductors 6.3 On-chip oscillator The on-chip oscillator provides the timing reference for the on-chip watchdog and the internal timers. The on-chip oscillator is supplied by an internal supply that is connected to V and is independent of V1. BAT 6.4 Watchdog (UJA1079/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms ...

  • Page 17

    ... NXP Semiconductors 6.4.2 Watchdog Timeout behavior The watchdog runs continuously in Timeout mode. It can be reset at any time by a watchdog trigger. If the watchdog overflows, the cyclic interrupt (CI) bit is set already pending, a system reset is performed. The watchdog is in Timeout mode when pin WDOFF is LOW and: • ...

  • Page 18

    ... NXP Semiconductors 6.5.1 RSTN pin A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a system reset is triggered internally. The reset pulse width (t generated undervoltage event (see (V > V BAT selected by connecting a 900 Ω ...

  • Page 19

    ... NXP Semiconductors 6.6 Power supplies 6.6.1 Battery pin (BAT) The SBC contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 4 The SBC can handle maximum voltages the voltage on pin BAT falls below the power-off detection threshold, V immediately enters Off mode, which means that the voltage regulator and the internal logic are shut down ...

  • Page 20

    ... NXP Semiconductors current current Fig 7. Figure 7 current of 250 mA with PDC = 0. Any additional load current requirement will be supplied by the PNP transistor its current limit. If the load current continues to rise, I increase above the selected PDC threshold (to a maximum of 250 mA). For a fast ramping load current, V1 will deliver the required load current (to a maximum of 250 mA) until the PNP transistor has switched on ...

  • Page 21

    ... The thermal performance of the transistor needs to be considered when calculating the value of this resistor. A 3.3 Ω resistor was used with the BCP52-16 (NXP Semiconductors) employed during testing. Note that the selection of the transistor is not critical. In general, any PNP transistor with a current amplification factor (β) of between 60 and 500 can be used ...

  • Page 22

    ... NXP Semiconductors The transmit data streams of the protocol controller at the TXDL input are converted by the transmitter into bus signals with optimized slew rate and wave shaping to minimize EME. 6.7.1.2 Lowpower/Off modes The LIN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit STBCL = 1 (see Lowpower mode ...

  • Page 23

    ... NXP Semiconductors Fig 9. The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are sampled continuously). The sampling will be performed on the rising edge of WBIAS (see Figure 9). The sampling time ms, is selected via the Wake Bias Control bit (WBC) in the Mode_Control register ...

  • Page 24

    ... NXP Semiconductors 6.9 Interrupt output Pin INTN is an active-LOW, open-drain interrupt output driven LOW when at least one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit in the Int_Status register interrupt status bit and not the pending wake-up. The pending wake-up is cleared on entering Normal mode and when the corresponding standby control bit (STBCL ...

  • Page 25

    ... NXP Semiconductors 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V voltage on pin reverse current from R(V1-BAT) pin V1 to pin BAT I current on pin DLIN DLIN V transient voltage trt V electrostatic ESD discharge voltage T virtual junction ...

  • Page 26

    ... NXP Semiconductors Table 8. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T ambient amb temperature [1] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (−). [2] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. ...

  • Page 27

    ... NXP Semiconductors 8. Thermal characteristics Fig 11. HTSSOP PCB UJA1079_2 Product data sheet PCB copper area: (bottom layer PCB copper area: (bottom layer measurements: board finish thickness 1.6 mm ±10 %, board double Layout conditions for R th(j-a) layer, board dimensions 129 mm × 60 mm, board Material FR4, Cu thickness 0.070 mm, thermal via separation 1.2 mm, thermal via diameter 0.3 mm ± ...

  • Page 28

    ... NXP Semiconductors R (K/W) Fig 12. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper Table 9. Symbol R th(j-a) [1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board. [2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the first inner copper layer ...

  • Page 29

    ... NXP Semiconductors 9. Static characteristics Table 10. Static characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Supply; pin BAT V battery supply voltage BAT I battery supply current BAT I additional battery supply BAT(add) current V power-on detection threshold ...

  • Page 30

    ... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter V power-on detection hysteresis hys(det)pon voltage V LIN undervoltage detection uvd(LIN) voltage V LIN undervoltage recovery uvr(LIN) voltage V LIN undervoltage detection hys(uvd)LIN hysteresis voltage ...

  • Page 31

    ... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Load regulation ΔV voltage variation on pin V1 V1 Line regulation ΔV voltage variation on pin V1 V1 PNP base; pin VEXCTRL I short-circuit output current ...

  • Page 32

    ... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Reset output with clamping detection; pin RSTN I HIGH-level output current OH I LOW-level output current OL V LOW-level output voltage OL V HIGH-level output voltage ...

  • Page 33

    ... NXP Semiconductors Table 10. Static characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter R pull-up resistance pu LIN receive data output; pin RXDL I HIGH-level output current OH I LOW-level output current OL R pull-up resistance pu LIN bus line; pin LIN ...

  • Page 34

    ... NXP Semiconductors 10. Dynamic characteristics Table 11. Dynamic characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter Voltage source; pin V1 t undervoltage detection delay d(uvd) time t LOW-level clamping detection det(CL)L time Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO ...

  • Page 35

    ... NXP Semiconductors Table 11. Dynamic characteristics − ° °C to +150 4 BAT positive currents flow in the IC; typical values are given at V Symbol Parameter δ2 duty cycle 2 δ3 duty cycle 3 δ4 duty cycle 4 t rising receiver propagation PD(RX)r delay t falling receiver propagation PD(RX)f delay ...

  • Page 36

    ... NXP Semiconductors max ( ) bus rec δ2 δ4 , ------------------------------- - = [3] . × bit − PD(RX)sym PD(RX)r PD(RX)f [5] A system reset will be performed if the watchdog is in Window mode and is triggered less than t period (or in the first half of the watchdog period). [6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Window mode only ...

  • Page 37

    ... NXP Semiconductors SCS t SPILEAD SCK SDI X floating SDO Fig 15. SPI timing diagram 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. ...

  • Page 38

    ... NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 0.95 mm 1.1 0.25 ...

  • Page 39

    ... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

  • Page 40

    ... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

  • Page 41

    ... NXP Semiconductors Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. UJA1079_2 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...

  • Page 42

    ... NXP Semiconductors 14. Revision history Table 14. Revision history Document ID Release date UJA1079_2 20100527 • Modifications: Template upgraded to Rev. 2.11 including revised legal information • Figure • Table • Table • Table • Table I • Table • Section UJA1079_1 20091201 UJA1079_2 Product data sheet ...

  • Page 43

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 44

    ... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: UJA1079_2 Product data sheet 15 ...

  • Page 45

    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Power management . . . . . . . . . . . . . . . . . . . . . 2 2.4 Control and Diagnostic features . . . . . . . . . . . . 2 2.5 Voltage regulator Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6 ...