TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 15

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
Table 6.
Table 7.
[1]
UJA1079_2
Product data sheet
Bit
0
Bit
15:13
12
11
10
9
8
7
6
5
4
3:0
An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.
Symbol
WSE2
Symbol
A2, A1, A0 R
RO
V1UI
reserved
LWI
reserved
CI
WI1
POSI
WI2
reserved
Int_Control register
Int_Status register
6.2.6 Int_Status register
Access Power-on
R/W
Access Power-on
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R
[1]
default
0
default
011
0
0
0
0
0
0
0
1
0
0000
All information provided in this document is subject to legal disclaimers.
Description
WAKE2 sample enable
Description
register address
access status
V1 undervoltage interrupts
LIN wake-up interrupt
cyclic interrupt
wake-up interrupt 1
power-on status interrupt
wake-up interrupt 2
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
0: register set to read/write
1: register set to read only
0: no V1 undervoltage warning interrupt pending
1: V1 undervoltage warning interrupt pending
0: no LIN wake-up interrupt pending
1: LIN wake-up interrupt pending
0: no cyclic interrupt pending
1: cyclic interrupt pending
0: no wake-up interrupt 1 pending
1: wake-up interrupt 1 pending
0: no power-on interrupt pending
1: power-on interrupt pending
0: no wake-up interrupt 2 pending
1: wake-up interrupt 2 pending
Rev. 02 — 27 May 2010
LIN core system basis chip
UJA1079
© NXP B.V. 2010. All rights reserved.
15 of 45