TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 21

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
UJA1079_2
Product data sheet
6.7.1.1 Active mode
6.7.1 LIN operating modes
6.7 LIN transceiver
For short-circuit protection, a resistor needs to be connected between pins V1 and
VEXCC to allow the current to be monitored. This resistor limits the current delivered by
the external transistor. If the voltage difference between pins VEXCC and V1 reaches
V
not increase further.
The thermal performance of the transistor needs to be considered when calculating the
value of this resistor. A 3.3 Ω resistor was used with the BCP52-16 (NXP Semiconductors)
employed during testing. Note that the selection of the transistor is not critical. In general,
any PNP transistor with a current amplification factor (β) of between 60 and 500 can be
used.
If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin
VEXCTRL can be left open.
One advantage of this scalable voltage regulator concept is that there are no PCB layout
restrictions when using the external PNP. The distance between the UJA1079 and the
external PNP doesn’t affect the stability of the regulator loop because the loop is realized
within the UJA1079. Therefore, it is recommended that the distance between the
UJA1079 and PNP transistor be maximized for optimal thermal distribution.
The output voltage on V1 is monitored continuously and a system reset signal is
generated if an undervoltage event occurs. A system reset is generated if the voltage on
V1 falls below the undervoltage detection voltage (V
threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit
(RTHC) in the Int_Control register
interrupt) will be generated at 90 % of the nominal output voltage. The status of V1 can be
read via bit V1S in the WD_and_Status register
The analog section of the UJA1079 LIN transceiver is identical to that integrated into the
TJA1021.
The transceiver is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates
from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.
The LIN transceiver will be in Active mode when:
In LIN Active mode, the transceiver can transmit and receive data via the LIN bus pin.
The receiver detects data streams on the LIN bus pin (LIN) and transfers them to the
microcontroller via pins RXDL (see
level on RXDL, LIN dominant by a LOW level.
th(act)Ilim
•
•
•
the SBC is in Normal mode (MC = 10 or 11) and
the transceiver is enabled (STBCL = 0; see
the battery voltage (V
, the PNP current limiting activation threshold voltage, the transistor current will
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
BAT
) is above the LIN undervoltage recovery threshold, V
(Table
Figure
6). In addition, an undervoltage warning (a V1UI
1) - LIN recessive is represented by a HIGH
(Table
Table
uvd
6) and
; see
4).
LIN core system basis chip
Table
10). The reset
UJA1079
© NXP B.V. 2010. All rights reserved.
uvr(LIN)
21 of 45
.