TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 22

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
UJA1079_2
Product data sheet
6.7.1.2 Lowpower/Off modes
6.7.2.1 General fail-safe features
6.7.2.2 TXDL dominant time-out function
6.7.2 Fail-safe features
6.8 Local wake-up input
The transmit data streams of the protocol controller at the TXDL input are converted by
the transmitter into bus signals with optimized slew rate and wave shaping to minimize
EME.
The LIN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit
STBCL = 1 (see
Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceiver
will be in Off mode if bit STBCL = 0. The LIN transceiver is powered down completely in
Off mode to minimize quiescent current consumption.
Filters at the receiver inputs prevent unwanted wake-up events due to automotive
transients or EMI.
The wake-up event must remain valid for at least the minimum dominant bus time for
wake-up of the LIN transceiver, t
The following fail-safe features have been implemented:
A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent
dominant state (blocking all network communications) if TXDL is forced permanently LOW
by a hardware and/or software application failure. The timer is triggered by a negative
edge on the TXDL pin. If the pin remains LOW for longer than the TXDL dominant
time-out time (t
state. The timer is reset by a positive edge on the TXDL pin.
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
•
•
•
Pin TXDL has an internal pull-up towards V
these pins are left floating
The current of the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin BAT
A loss of power (pins BAT and GND) has no impact on the bus lines or on the
microcontroller. There will be no reverse currents from the bus.
to(dom)TXDL
All information provided in this document is subject to legal disclaimers.
Table
6). The LIN transceiver can be woken up remotely via pin LIN in
Rev. 02 — 27 May 2010
), the transmitter is disabled, driving the bus lines to a recessive
wake(busdom)min
Table
6). These bits can also be used to disable
(see
V1
to guarantee safe, defined states if
Table
11).
LIN core system basis chip
(Table
4).
UJA1079
© NXP B.V. 2010. All rights reserved.
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