ADSP-21266SKBCZ-2B Analog Devices Inc, ADSP-21266SKBCZ-2B Datasheet
ADSP-21266SKBCZ-2B
Specifications of ADSP-21266SKBCZ-2B
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ADSP-21266SKBCZ-2B Summary of contents
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... On-chip memory— bits on-chip SRAM and a dedi- cated 4M bits on-chip mask-programmable ROM The ADSP-2126x processors are available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see DUAL PORTED MEMORY ...
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... ADSP-21261/ADSP-21262/ADSP-21266 TABLE OF CONTENTS Summary ............................................................... 1 Table of Contents ..................................................... 2 Revision History ...................................................... 2 General Description ................................................. 3 Family Core Architecture ........................................ 3 Memory and I/O Interface Features ........................... 4 Target Board JTAG Emulator Connector .................... 8 Development Tools ............................................... 8 Evaluation Kit ...................................................... 9 Designing an Emulator-Compatible DSP Board (Target) 9 Additional Information .......................................... 9 Pin Function Descriptions ....................................... 10 Address Data Pins as Flags .................................... 13 Core Instruction Rate to CLKIN Ratio Modes ...
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... Assumes two files in multichannel SIMD mode. As shown in the functional block diagram in the ADSP-2126x uses two computational units to deliver times performance increase over previous SHARC proces- sors on a range of DSP algorithms. Fabricated in a state-of-the- art, high speed, CMOS process, the ADSP-2126x DSPs achieve an instruction cycle time 200 MHz or 6 ...
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... Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-2126x can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction ...
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... The ADSP-2126x’s SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float- ing-point storage format is supported that effectively doubles the amount of data that can be stored on-chip ...
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... The DAI also includes six serial ports, two precision clock gen- erators (PCGs), an input data port (IDP), six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-2126x core, configurable as either eight 2 channels serial data seven channels plus a single 20-bit wide synchronous parallel data acquisition port ...
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... Timers The ADSP-2126x has a total of four timers: a core timer able to generate periodic software interrupts, and three general-pur- pose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
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... TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-2126x pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG ...
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... This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2126x architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer ®† ...
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... ADSP-21261/ADSP-21262/ADSP-21266 PIN FUNCTION DESCRIPTIONS The ADSP-2126x pin definitions are listed below. Inputs identi- fied as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchro- nously to CLKIN (or to TCK for TRST). Tie or pull unused ...
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... If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode. SPI Master In Slave Out. If the ADSP-2126x is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-2126x is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2126x. TRST has a 22.5 k internal pull-up resistor. Emulation Status. Must be connected to the ADSP-2126x Analog Devices DSP Tools product line of JTAG emulators target board connector only ...
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... Reserved ADSP-21261/ADSP-21262/ADSP-21266 ADDRESS DATA MODES Table 10 shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit data transfers, ALE latches address bits A15– ...
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... ADSP-21261/ADSP-21262/ADSP-21266 PRODUCT SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Input Voltage _ IH CLKIN V Low Level Input Voltage @ V ...
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... PACKAGE INFORMATION The information presented in Figure 3 the package branding for the ADSP-21266 processors. For a complete listing of product availability, see Page 44. a ADSP-2126x tppZ-cc vvvvvv.x n.n #yyww country_of_origin S Figure 3. Typical Package Brand Table 11. Package Brand Information Brand Key Field Description t Temperature Range ...
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... The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-2126x SHARC Processor Peripherals Reference and Managing the Core PLL on Third- Table 13 Generation SHARC Processors (EE-290). ...
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... The 4096 cycle count depends on t specification in SRST 4097 cycles maximum. RESET V DDINT V DDEXT CLKIN CLK_CFG1–0 RESETOUT (MULTIPLEXED WITH CLKOUT) ADSP-21261/ADSP-21262/ADSP-21266 Table DDINT DDEXT DDEXT 1 /V Valid DDINT DDEXT Table 17. If setup time is not met, one additional CLKIN cycle can be added to the core reset time, resulting in ...
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... CKH Figure 6. Clock Input Clock Signals The ADSP-2126x can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-2126x to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun- damental mode ...
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... Table 18 and FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins when configured as interrupts. Table 18. Interrupts Parameter Timing Requirements t IRQx Pulse Width IPW ADSP-21261/ADSP-21262/ADSP-21266 Min WRST Figure 8. Reset Figure 9 applies to the DAI_P20– ...
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... ADSP-21261/ADSP-21262/ADSP-21266 Core Timer The timing specification in Table 19 and FLAG3 when it is configured as the core timer (CTIMER). Table 19. Core Timer Parameter Switching Characteristics t CTIMER Pulse Width WCTIM TIM Timer PWM_OUT Cycle Timing The timing specification in Table 20 and Timer in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20– ...
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... Figure 13 for direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 22. DAI Pin-to-Pin Routing Parameter Timing Requirements t Delay DAI Pin Input Valid to DAI Output Valid DPIO ADSP-21261/ADSP-21262/ADSP-21266 Figure 12 applies to Min 2 × t CCLK t PWI Figure 12. Timer Width Capture Timing DAI_Pn DAI_Pm ...
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... ADSP-21261/ADSP-21262/ADSP-21266 Precision Clock Generator (Direct Pin Routing) The timing in Table 23 and Figure 14 is valid only when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buff- ers) and sends its outputs directly to the DAI pins. For the other Table 23 ...
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... Table 24. Flags Parameter Timing Requirements t FLAG3–0 IN Pulse Width FIPW Switching Characteristics t FLAG3–0 OUT Pulse Width FOPW DAI_P20–1 (FLAG3–0 DAI_P20–1 (FLAG3–0 ADSP-21261/ADSP-21262/ADSP-21266 Figure 15 apply to the for more informa (AD15–0) t FIPW ) OUT (AD15–0) t FOPW Figure 15. Flags Rev ...
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... ADSP-21261/ADSP-21262/ADSP-21266 Memory Read—Parallel Port The specifications in Table 25, Table 26, Figure 17 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2126x is access- ing external memory space. Table 25. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 7–0 Setup Before RD High DRS t Address/Data 7–0 Hold After RD High ...
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... D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × (if a hold cycle is specified, else CCLK 1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low. ALE RD WR AD15-0 ADSP-21261/ADSP-21262/ADSP-21266 CCLK t ALEW t ALERW t ADAH t ADAS VALID ADDRESS ...
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... ADSP-21261/ADSP-21262/ADSP-21266 Memory Write—Parallel Port Use the specifications in Table 27, Table Figure 19 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2126x is access- ing external memory space. Table 27. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ...
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... DWH D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × (if a hold cycle is specified, else CCLK 1 On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low. ALE WR RD AD15 - 0 ADSP-21261/ADSP-21262/ADSP-21266 CCLK t ALEW t ALERW t t ALEH t t ...
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... ADSP-21261/ADSP-21262/ADSP-21266 Serial Ports To determine whether communication is possible between two devices at a given clock speed, the specifications in Table 30, Table 31, Table 32, Figure 20, and confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) SCLK width. ...
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... DAI_P20-1 (FS) DAI_P20-1 (DATA CHANNEL A/B) NOTE: SERIAL PORT SIGNALS (SCLK, FS, USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS. 1 This figure reflects changes made to support left-justified sample pair mode. ADSP-21261/ADSP-21262/ADSP-21266 EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE ...
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... ADSP-21261/ADSP-21262/ADSP-21266 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t DAI_P20–1 (SCLK) t DFSI t HOFSI DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE t DAI_P20– ...
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... Clock Period IDPCLK 1 DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either CLKIN or any of the DAI pins. DAI_P20 DAI_P20 DAI_P20 ADSP-21261/ADSP-21262/ADSP-21266 Table 33 and SAMPLE EDGE ...
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... The timing requirements for the PDAP are provided in and Figure 23. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Table 34. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements t ...
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... SPITDM FLG3-0 (OUTPUT SPICLK ( (OUTPUT SPICLK ( (OUTPUT) MOSI (OUTPUT) CPHASE = 1 MISO MSB (INPUT) VALID MOSI MSB (OUTPUT CPHASE = 0 MSB MISO VALID (INPUT) ADSP-21261/ADSP-21262/ADSP-21266 HDSPIDM MSB LSB VALID Figure 24. SPI Interface Protocol—Master Rev Page July 2009 Min Max × t CCLK 4 × t – ...
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... ADSP-21261/ADSP-21262/ADSP-21266 SPI Interface Protocol—Slave Table 36. SPI Interface Protocol—Slave Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 t Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0 ...
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... System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0. 2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE. TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS ADSP-21261/ADSP-21262/ADSP-21266 Min × ...
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... ADSP-21261/ADSP-21262/ADSP-21266 OUTPUT DRIVE CURRENTS Figure 27 shows typical I-V characteristics for the output driv- ers of the ADSP-2126x. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125°C 0 –10 3.11V, 125°C –20 – 3.47V, –45°C – ...
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... LOAD CAPACITANCE (pF) Figure 32. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) ENVIRONMENTAL CONDITIONS The ADSP-2126x processor is rated for performance under T environmental conditions specified in the tions on Page 14. THERMAL CHARACTERISTICS Table 38 and Table 39 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... ADSP-21261/ADSP-21262/ADSP-21266 144-LEAD LQFP PIN CONFIGURATIONS Table 40 shows the ADSP-2126x’s pin names and their default function after reset (in parentheses). Table 40. 144-Lead LQFP Pin Assignments LQFP Pin Name Pin No. Pin Name DDINT DDINT CLK_CFG0 2 GND CLK_CFG1 3 RD BOOT_CFG0 4 ALE BOOT_CFG1 5 AD15 GND ...
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... BGA PIN CONFIGURATIONS Table 41 shows the ADSP-2126x’s pin names and their default function after reset (in parentheses). Figure 33 on Page 41 shows the BGA package pin assignments. Table 41. 136-Ball BGA Pin Assignments BGA Pin Pin Name No. Pin Name CLK_CFG0 A01 CLK_CFG1 ...
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... ADSP-21261/ADSP-21262/ADSP-21266 Table 41. 136-Ball BGA Pin Assignments (Continued) BGA Pin Pin Name No. Pin Name AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) ...
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... ADSP-21261/ADSP-21262/ADSP-21266 KEY V A GND DDINT VDD V A I/O SIGNALS DDEXT VSS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 33. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev Page July 2009 ...
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... ADSP-21261/ADSP-21262/ADSP-21266 OUTLINE DIMENSIONS The ADSP-2126x is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 35 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW and Figure 34. 0.75 1.60 0.60 MAX 0.45 144 1 PIN 1 0.20 0.09 7° 3.5° ...
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... PCB design. For industry- standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 42. BGA_ED Data for Use with Surface-Mount Design Package Ball Attach Type 136-Ball CSP_BGA (BC-136) Solder Mask Defined (SMD) ADSP-21261/ADSP-21262/ADSP-21266 12.10 12. 11. BALL A1 INDICATOR 10 ...
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... ADSP-21261SKBCZ150 + ADSP-21261SKSTZ150 +70 C ADSP-21262SBBC-150 – + ADSP-21262SBBCZ150 – +85 C ADSP-21262SKBC-200 + ADSP-21262SKBCZ200 + ADSP-21262SKSTZ200 + ADSP-21266SKSTZ- + ADSP-21266SKSTZ- + ADSP-21266SKBCZ- + ADSP-21266SKSTZ- + ADSP-21266SKSTZ- + ADSP-21266SKBCZ- + ADSP-21266SKSTZ- + ADSP-21266SKSTZ- + ADSP-21266SKBCZ- + Referenced temperature is ambient temperature RoHS Compliant Part end of part number indicates Rev. 0.1 silicon. See 4 C and D at end of part number indicate Rev. 0.2 silicon. See © ...