TDA7575B STMicroelectronics, TDA7575B Datasheet - Page 16

• Manufacturer Part Number: TDA7575B
• Description: IC AMP DUAL BRIDGE FLEXIWATT27
• Manufacturer: STMicroelectronics
• Type: Class ABr

Specifications of TDA7575B

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 150W x 1 @ 1 Ohm; 75W x 2 @ 2 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: Differential Inputs, I²C, Mute, Short-Circuit and Thermal Protection, Standby
• Mounting Type: Through Hole
• Package / Case: 27-Flexiwatt (bent and staggered leads)
• Operational Class: Class-AB
• Audio Amplifier Output Configuration: 1-Channel Mono/2-Channel Stereo
• Output Power (typ): 150x1@1Ohm/75x2@2OhmW
• Audio Amplifier Function: Speaker
• Input Offset Voltage: 45@14.4VmV
• Total Harmonic Distortion: 0.02@4Ohm@30W%
• Single Supply Voltage (typ): 9/12/15V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Single
• Power Dissipation: 86W
• Rail/rail I/o Type: No
• Single Supply Voltage (min): 8V
• Single Supply Voltage (max): 18V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -55C to 150C
• Operating Temperature Classification: Military
• Mounting: Through Hole
• Pin Count: 27
• Package Type: FLEXIWATT(Vertical)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I2C bus interface
5
5.1
5.2
5.3
5.4
16/32
I
Data transmission from microprocessor to the TDA7575B and vice versa takes place
through the 2 wires I
resistors to positive supply voltage must be connected).
Data validity
As shown by
the clock.
The high and low state of the data line can only change when the clock signal on the SCL
line is low.
Start and stop conditions
As shown by
is high.
The stop condItion Is A Low To High Transition of the SDA line while SCL is high.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The transmitter
pulse (see
line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock
pulse.
(*) Transmitter
(**) Receiver
Figure 26. Data validity on the I
2
C bus interface
= master (μP) when it writes an address to the TDA7575B
= slave (TDA7575B) when the µP reads a data byte from TDA7575B
= slave (TDA7575B) when the µP writes an address to the TDA7575B
= master (μP) when it reads a data byte from TDA7575B
Figure
Figure
Figure 27
SDA
(*)
SCL
puts a resistive HIGH level on the SDA line during the acknowledge clock
28). The receiver
2
26, the data on the SDA line must be stable during the high period of
C BUS interface, consisting of the two lines SDA and SCL (pull-up
a start condition is a high to low transition of the SDA line while SCL
STABLE, DATA
DATA LINE
Doc ID 14103 Rev 2
VALID
2
(**)
C bus
the acknowledges has to pull-down (LOW) the SDA
ALLOWED
CHANGE
DATA
D99AU1031
TDA7575B