• Industry Standard Pinout
• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA
= 5V and Cycle Time = 1 s
• Two Chip Select Inputs Simple Memory Expansion
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
• Output Disable for Common I/O Systems
• Three-State Data Output for Bus Oriented Systems
• Separate Data Inputs and Outputs
• TTL Compatible (MWS5101A)
C to +70
C to +70
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, CDP1822 may be used.
The MWS5101 and MWS5101A types are supplied in 22
lead hermetic dual-in-line, sidebrazed ceramic packages (D
sufﬁx), in 22 lead dual-in-line plastic packages (E sufﬁx), and
in chip form (H sufﬁx).
Intersil Corporation 1999
256-Word x 4-Bit
LSI Static RAM