MWS5101EL2

Manufacturer Part NumberMWS5101EL2
ManufacturerIntersil Corporation
MWS5101EL2 datasheet
 


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March 1997
Features
• Industry Standard Pinout
• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA
at V
= 5V and Cycle Time = 1 s
DD
• Two Chip Select Inputs Simple Memory Expansion
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
• Output Disable for Common I/O Systems
• Three-State Data Output for Bus Oriented Systems
• Separate Data Inputs and Outputs
• TTL Compatible (MWS5101A)
Pinout
MWS5101, MWS5101A
(PDIP, SBDIP)
TOP VIEW
1
A3
2
A2
3
A1
4
A0
A5
5
6
A6
A7
7
V
8
SS
9
DI1
DO1
10
11
DI2
Ordering Information
PACKAGE
TEMP. RANGE
o
o
PDIP
0
C to +70
Burn-In
o
o
SBDIP
0
C to +70
Burn-In
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
http://www.intersil.com or 407-727-9207
Copyright
Description
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
22
V
DD
static RAM, CDP1822 may be used.
A4
21
The MWS5101 and MWS5101A types are supplied in 22
R/W
20
lead hermetic dual-in-line, sidebrazed ceramic packages (D
CSI
19
suffix), in 22 lead dual-in-line plastic packages (E suffix), and
O.D.
18
in chip form (H suffix).
CS2
17
DO4
16
DI4
15
DO3
14
DI3
13
DO2
12
MWS5101
250ns
350ns
C
MWS5101EL2
MWS5101ELS
C
-
MWS5101DL3X
©
Intersil Corporation 1999
6-56
MWS5101,
MWS5101A
256-Word x 4-Bit
LSI Static RAM
MWS5101A
250ns
350ns
PKG. NO.
MWS5101AEL2
MWS5101AEL3
E22.4
MWS5101AEL3X E22.4
-
MWS5101ADL3
D22.4A
D22.4A
File Number
1106.2

MWS5101EL2 Summary of contents