MSC7113 Motorola, MSC7113 Datasheet

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MSC7113

Manufacturer Part Number
MSC7113
Description
Manufacturer
Motorola
Datasheet

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Freescale Semiconductor
Data Sheet
Low-Cost 16-bit DSP with
DDR Controller and 10/100
Mbps Ethernet MAC
• StarCore
• 8 Kbyte boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
• Internal PLL generates up to 266 MHz clock for the SC1400 core
• Clock synthesis module provides predivision of PLL input clock;
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
• DDR memory controller that supports byte enables for up to a
• Programmable memory interface with independent read buffers,
• System control unit performs software watchdog timer function;
• Event port collects and counts important signal events including
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
and up to 133 MHz for the crossbar switch, DMA channels, M2
memory, and other peripherals.
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
32-bit data bus; glueless interface to 133 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
programmable predictive read feature for each buffer, and a write
buffer.
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
®
SC1400 DSP extended core with one SC1400 DSP
• Multi-channel DMA controller with 32 time-multiplexed
• Two independent TDM modules with independent receive and
• Ethernet controller with support for 10/100 Mbps MII/RMII
• UART with full-duplex operation up to 5.0 Mbps.
• Up to 41 general-purpose input/output (GPIO) ports.
• I
• Two quad timer modules, each with sixteen configurable 16-bit
• fieldBIST™ unit detects and provides visibility into unlikely field
• Standard JTAG interface allows easy integration to system
• Optional booting external host via 8-bit or 16-bit access through
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™,
and 802.3ac™; with internal receive and transmit FIFOs and a
FIFO controller; direct access to internal memories via its own
DMA controller; full and half duplex operation; programmable
maximum frame length; virtual local area network (VLAN) tag
and priority support; retransmission of transmit FIFO following
collision; CRC generation and verification for inbound and
outbound packets; and address recognition including
promiscuous, broadcast, individual address. hash/exact match,
and multicast hash match.
Mbyte.
timers.
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
firmware and internal on-chip emulation (OCE10) module.
the HDI16, I
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
2
C interface that allows booting from EEPROM devices up to 1
2
C, or SPI using in the boot ROM to access serial SPI
MSC7113
Document Number: MSC7113
MAP-BGA–400
17 mm × 17 mm
Rev. 11, 4/2008

Related parts for MSC7113

MSC7113 Summary of contents

Page 1

... DMA and interrupt requests and trigger events such as interrupts, breakpoints, DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC7113 MSC7113 MAP-BGA–400 17 mm × • Multi-channel DMA controller with 32 time-multiplexed ...

Page 2

... Package Information .57 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 www.DataSheet4U.com List of Figures Figure 1. MSC7113 Block Diagram Figure 2. MSC7113 Molded Array Process-Ball Grid Array (MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. MSC7113 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Timing Diagram for a Reset Configuration Write . . . . 24 Figure 5 ...

Page 3

... KB) 128 AMEC Extended Core 64 Interface M1 SRAM ASM1 (192 KB AMENT Ethernet MAC MII/RMII Figure 1. MSC7113 Block Diagram MSC7113 Data Sheet, Rev. 11 ASM2 128 Boot ROM (8 KB) ASEMI External Bus External Memory from 64 32 Interface IPBus Interrupts Interrupt Control Host HDI16 Interface ...

Page 4

... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC7113 package ball grid array layouts and pinout allocation tables. 1.1 MAP-BGA Ball Layout Diagrams Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers. ...

Page 5

... DDPLL R TEST0 EE0 TDO T TMS MDIO HRESET U TRST TCK COL V TDI CRS TX_EN W MDC RX_ER TXCLK Y RX_DV GND RXD1 Figure 3. MSC7113 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View Freescale Semiconductor Bottom View GND HD0 HD1 HD4 HD6 HD2 HD5 HD8 ...

Page 6

... A16 (1M88B) BM3 A17 A18 A19 A20 B10 B11 B12 B13 B14 6 Table 1. MSC7113 Signals by Ball Designator Signal Names Software Controlled GPI Enabled Interrupt GPO Enabled (Default) Enabled GND GND DQM1 DQS2 CK CK GPIC7 GPIC4 GPIC2 reserved reserved reserved reserved reserved ...

Page 7

... C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D10 D11 Freescale Semiconductor Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled GPID7 DQM3 DQM0 DQS1 RAS CAS GPIC5 GPIC1 reserved V GND MSC7113 Data Sheet, Rev ...

Page 8

... D16 D17 D18 D19 D20 E1 www.DataSheet4U.com E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled GND GND GND GND MSC7113 Data Sheet, Rev. 11 Hardware Controlled ...

Page 9

... G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 Freescale Semiconductor Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled V V GND GND GND GND GND V V GND GND GND GND GND GND ...

Page 10

... J10 J11 J12 J13 J14 J15 J16 J17 J18 (1L44X) J18 (1M88B) J19 J20 HDSP Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled GND GND GND GND GND GND GND reserved reserved GND GND ...

Page 11

... L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 (1L44X) L18 (1M88B) L19 L20 M1 Freescale Semiconductor Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled V GND GND GND GND GND GND GND GND GND ...

Page 12

... M18 M19 M20 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 12 Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled GND GND GND GND GND GND GND GND GND GND V V GPIA14 IRQ15 ...

Page 13

... P15 P16 P17 P18 P19 P20 R10 R11 R12 R13 R14 R15 R16 R17 Freescale Semiconductor Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled GND GND GND GND GND GND GND GND PORESET TPSEL ...

Page 14

... T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U10 U11 U12 U13 U14 U15 14 Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled TDO reserved TEST0 reserved TMS HRESET GND V ...

Page 15

... V15 V16 V17 V18 V19 V20 W10 BM0 W11 W12 W13 Freescale Semiconductor Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled V V reserved TCK TRST V reserved GPIA16 IRQ12 GPIA8 IRQ6 GPIA4 IRQ1 GPIA0 IRQ11 ...

Page 16

... BM1 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 16 Table 1. MSC7113 Signals by Ball Designator (continued) Signal Names Software Controlled GPI Enabled Interrupt (Default) Enabled GPIA1 IRQ10 GPID4 GPIA27 IRQ18 GPIA19 IRQ19 GPIA23 IRQ23 GPIA26 IRQ26 reserved V GND ...

Page 17

... Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC7113. Core supply voltage Memory supply voltage ...

Page 18

... Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Reference voltage Operating temperature range 2.3 Thermal Characteristics www.DataSheet4U.com Table 4 describes thermal characteristics of the MSC7113 for the MAP-BGA package. Characteristic 1, 2 Junction-to-ambient Junction-to-ambient, four-layer board 4 Junction-to-board 5 Junction-to-case 6 ...

Page 19

... V REF exceed ±2% of the DC value not applied directly to the MSC7113 device the level measured at the far end signal termination. It should be equal This rail should track variations in the DC level of V REF Output leakage for the memory interface is measured with all outputs disabled ≤ ...

Page 20

... CLKO frequency jitter (peak-to-peak) 2.5.2 Configuring Clock Frequencies This section describes important requirements for configuring clock frequencies in the MSC7113 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL): • PLLDVF field. Specifies the PLL division factor. The output of the divider block is the input to the multiplier block. ...

Page 21

... The minimum and maximum multiplication factors are dependent on the Loop Table 11. F Frequency Ranges vco Allowed Range which is F modified by CLKCTRL[RNG]. vco Loop MSC7113 Data Sheet, Rev. 11 Electrical Characteristics Comments Maximum PLLMLTF Value 532/Divided Input Clock vco 266 ≤ F ≤ 532 MHz vco 133 ≤ F ≤ ...

Page 22

... Reset Timing The MSC7113 device has several inputs to the reset logic. All MSC7113 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset ...

Page 23

... PORESET initiates the power-on reset flow. external power to the MSC7113 reaches at least 2/3 2.5.3.2 Reset Configuration The MSC7113 has two mechanisms for writing the reset configuration: • From a host through the host interface (HDI16) • From memory through the I Five signal levels (see Chapter 1 for signal description details) are sampled on operating conditions: • ...

Page 24

... Figure 4. Timing Diagram for a Reset Configuration Write Table 17. DDR DRAM Input AC Timing Symbol — — value. CK 202 202 D0 D1 201 Figure 5. DDR DRAM Input Timing Diagram MSC7113 Data Sheet, Rev Max Min Mask Set Mask Set 1L44X 1M88B — V – 0.31 V – 0.31 REF REF + 0. 0 ...

Page 25

... DDKHCX t DDKHMH 3 t DDKHDS, t DDKLDS 3 t DDKHDX, t DDKLDX 4 t DDKHMP 5 t DDKHME MSC7113 Data Sheet, Rev. 11 Electrical Characteristics Min Max Mask Set Mask Set 1L44X 1M88B 10 1.0 — Not applicable 7.52 — 0.5 × t 0.5 × t – 2250 – 1000 — ...

Page 26

... D0 D1 210 Figure 6. DDR DRAM Output Timing Diagram = 50 Ω Output Z 0 Figure 7. DDR DRAM AC Test Load Table 19. DDR DRAM Measurement Conditions Symbol Table 20. TDM Timing Characteristic MSC7113 Data Sheet, Rev. 11 212 210 V OUT = 50 Ω DDR DRAM V ± 0.31 V REF 0.5 × V ...

Page 27

... TDMxRD 305 303 310 Figure 8. TDM Receive Signals 301 307 306 305 303 Figure 9. TDM Transmit Signals MSC7113 Data Sheet, Rev. 11 Electrical Characteristics Expression Min Max — 14.0 2.0 — — 10.0 — 13.5 2.5 — 302 ...

Page 28

... Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time www.DataSheet4U.com Receive clock RXDn RX_DV CRS_DV RX_ER 28 Table 21. Receive Signal Timing Characteristics 800 802 803 Valid Figure 10. Ethernet Receive Signal Timing MSC7113 Data Sheet, Rev. 11 Min Max Unit 40 — — — — ...

Page 29

... CRS COL CRS_DV Freescale Semiconductor Table 22. Transmit Signal Timing Characteristics 800 801 806 805 Figure 11. Ethernet Receive Signal Timing Table 23. Asynchronous Input Signal Timing Characteristics Figure 12. Asynchronous Input Signal Timing MSC7113 Data Sheet, Rev. 11 Electrical Characteristics Min Max Unit 40 — — — ...

Page 30

... MDC rising edge to MDIO input hold time www.DataSheet4U.com MDC (output) MDIO (output) MDIO (input) 30 Table 24. Ethernet Controller Management Interface Timing Characteristics 809 813 814 Figure 13. Serial Management Channel Timing MSC7113 Data Sheet, Rev. 11 Min Max 400 160 160 0 — 808 810 ...

Page 31

... (2.0 × (3.0 × 5,8,10 (3.0 × T (2.0 × T (5.0 × T MSC7113 Data Sheet, Rev. 11 Electrical Characteristics 1, 2 Mask Set 1L44X Mask Set 1M88B Expression Value Expression T Note 1 T HCLK CORE 3.0 × T Note 11 2.0 × 9.0 Note 11 ...

Page 32

... HCS[1–2] 57 HRW 44a HDS HD[0–15] Figure 14. Read Timing Diagram, Single Data Strobe MSC7113 Data Sheet, Rev (continued) Mask Set 1L44X Mask Set 1M88B Expression Value Expression = core clock period. At 266 MHz 3.75 ns. CORE = 0 pF for minimum delay timings. ...

Page 33

... HTRQ (double host request) Freescale Semiconductor HA[0– HCS[1–2] 44a HRD HD[0–15] Figure 15. Read Timing Diagram, Double Data Strobe HA[0– HCS[1–2] 57 HRW 45 HDS 47 HD[0–15] Figure 16. Write Timing Diagram, Single Data Strobe MSC7113 Data Sheet, Rev 44a ...

Page 34

... HCS[1–2] HWR 47 HD[0–15] Figure 17. Write Timing Diagram, Double Data Strobe HREQ (Output) 64 44a RX[0–3] HACK Read 50 49 HD[0–15] (Output) Figure 18. Host DMA Read Timing Diagram, HPCR[OAD MSC7113 Data Sheet, Rev 44b 51 52 Data Valid Freescale Semiconductor ...

Page 35

... Freescale Semiconductor HREQ (Output TX[0–3] Write HACK 47 HD[0–15] (Input) Figure 19. Host DMA Write Timing Diagram, HPCR[OAD MSC7113 Data Sheet, Rev Data Valid 35 ...

Page 36

... Data Byte 458 Data Byte 2 Figure 20 Timing Diagram MSC7113 Data Sheet, Rev. 11 Fast Min Max 0 400 — — — 2 × 1/F — BCK 0 — 250 — — 700 — ...

Page 37

... Figure 21. UART Input Timing 402 Figure 22. UART Output Timing Table 28. EE0 Timing Characteristics Asynchronous Synchronous to core clock EE pin. EE0 in EE0 out Figure 23. EE Pin Timing MSC7113 Data Sheet, Rev. 11 Mask Set Mask Set 1L44X 1M88B Min Max Min F /2 — 100 — ...

Page 38

... Table 30. GPIO Signal Timing Characteristics Asynchronous Synchronous to core clock Asynchronous Asynchronous GPI/GPO pin. GPI GPO Figure 25. GPI/GPO Pin Timing MSC7113 Data Sheet, Rev. 11 Type Min 1.5 × APBCLK periods 1 APBCLK period 67 68 1,2,3 Type Min 1.5 × APBCLK periods 1 APBCLK period 1.5 × ...

Page 39

... All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. TCK (Input) Freescale Semiconductor Table 31. JTAG Timing Characteristics × 3); maximum 22 MHz 701 703 Figure 26. Test Clock Input Timing Diagram MSC7113 Data Sheet, Rev. 11 All frequencies Unit Min Max 0.0 40.0 MHz 25.0 — ns 11.0 — ns 0.0 3.0 ns 5.0 — ...

Page 40

... Figure 27. Boundary Scan (JTAG) Timing Diagram V IL 710 Output Data Valid 711 Figure 28. Test Access Port Timing Diagram 712 Figure 29. TRST Timing Diagram MSC7113 Data Sheet, Rev 704 705 Input Data Valid Output Data Valid V IH 709 708 Input Data Valid ...

Page 41

... I/O The power dissipation values for the MSC7113 are listed in Table 4. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the www ...

Page 42

... Reference I/O www.DataSheet4U.com You should supply the MSC7113 core voltage via a variable switching supply or regulator to allow for compatibility with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across V and and the I/O section is supplied with 3.3 V (± 10%) across V GND the DDR memory controller block ...

Page 43

... V) supply fourth (last). (1.25 V) supply first. (2.5 V) supply second. (1.2 V) supply third. (3.3 V) supply fourth (last). Time Figure 30. Voltage Sequencing Case 1 MSC7113 Data Sheet, Rev. 11 Hardware Design Considerations and V is less than 10 ms. DDIO DDC and V is less than 10 ms for ...

Page 44

... V) supplies simultaneously (second). DDM (1.25 V) supply last (third). (1.25 V) supply first. (2.5 V) supply second. (1.2 V) supply third. (3.3 V) supply fourth (last). Time Figure 31. Voltage Sequencing Case 2 MSC7113 Data Sheet, Rev. 11 and less than 10 ms. DDIO DDC DDM and V is less than 10 ms. ...

Page 45

... REF DDIO (2.5 V) and V (1.25 V) supplies simultaneously (first). REF (1.2 V) supply second. (3.3 V) supply third (last). Time Figure 32. Voltage Sequencing Case 3 MSC7113 Data Sheet, Rev. 11 Hardware Design Considerations and V is less than 10 ms. DDC and V is less than 10 ms. DDIO DDC ...

Page 46

... DDM REF DDIO (1.2 V), V (1.25 V), and V (2.5 V) supplies simultaneously (first). REF DDM (3.3 V) supply last. Time Figure 33. Voltage Sequencing Case 4 MSC7113 Data Sheet, Rev. 11 and V is less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down V DDIO ...

Page 47

... V) supply fourth (last). (1.25 V) supply first. (1.2 V) supply second. (2.5 V) supply third. (3.3 V) supply fourth (last). Time Figure 34. Voltage Sequencing Case 5 MSC7113 Data Sheet, Rev. 11 Hardware Design Considerations and V is less than 10 ms. DDIO DDM and V is less than 10 ms. ...

Page 48

... The second decoupling level should consist of two bulk/tantalum decoupling capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7113 voltage pins. Additionally, the maximum drop between the power supply and the DSP device should ...

Page 49

... V) 2 × 200 MHz × CORE = 750 pF × (1 × 266 MHz × CORE MSC7113 Data Sheet, Rev. 11 Hardware Design Considerations Nominal Voltage Current Rating 1.2 V 1.5 A per device 2.5 V 0.5 A per device 1. µA per device 3.3 V 1.0 A per device ...

Page 50

... Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage, termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7113 device, the 2.5 V power source provides the power for the termination, which is a static value per signal driven high. ...

Page 51

... Either a smaller value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7113 output current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design). ...

Page 52

... ROM. After initialization, the DSP core can enable the PLL and start the device operating at a higher speed. The MSC7113 can boot from an external host through the HDI16 or download a user program through the I by configuring the BM[1– ...

Page 53

... For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual. 3.5 DDR Memory System Guidelines MSC7113 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown in Figure 36 ...

Page 54

... Figure 37. SSTL Power Value Design Constraints TT DC offsets. Although they are isolated supplies, one possible solution is to use a REF and shield it with a ground trace. island and ensure a good, solid connection. TT MSC7113 Data Sheet, Rev Receiver V REF as a high current power source. This section outlines TT ...

Page 55

... Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages. Freescale Semiconductor + ) on the same layer. Avoid switching layers within a byte group. DQS DM MSC7113 Data Sheet, Rev. 11 Hardware Design Considerations 55 ...

Page 56

... Ordering Information 3.6 Connectivity Guidelines This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7113 device. Following are guidelines for signal groups and configuration settings: • Clock and reset signals. — SWTE is used to configure the MSC7113 device and is sampled on the deassertion of ...

Page 57

... MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7113 device. • SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock registers, program control, and instruction set ...

Page 58

... The power-up and power-down sequences have been expanded to five possible design scenarios/cases. These cases replace the previously recommended power-up/power-down sequence recommendations. The section has been clarified by adding subsection headings. • Change the PLL filter resistor from 20 Ω Ω in Section 3.2.5. MSC7113 Data Sheet, Rev. 11 Description Freescale Semiconductor ...

Page 59

... Freescale Semiconductor MSC7113 Data Sheet, Rev. 11 Revision History 59 ...

Page 60

... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MSC7113 Rev. 11 4/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...

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