SN74BCT29834NT

Manufacturer Part NumberSN74BCT29834NT
Description8-BIT TO 9-BIT PARITY TRANSCEIVERS
ManufacturerTexas Instruments, Inc.
SN74BCT29834NT datasheet
 


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BiCMOS Process With TTL Inputs and
Outputs
BiCMOS Design Reduces Standby Current
Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
Functionally Equivalent to SN74ALS29834
and AMD Am29834
High-Speed Bus Transceiver With Parity
Generator/ Checker
Parity-Error Flag With Open-Collector
Output
Available Register For Storage of the
Parity-Error Flag
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK
input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are
low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced
error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides
inverting logic.
The SN74BCT29834 is characterized for operation from 0 C to 70 C.
INPUTS
Ai
CLK
OEB
OEA
CLR
of H’s
Odd
L
H
X
X
Even
H
L
H
NA
X
X
L
X
X
H
No
X
L
No
X
H
H
H
Odd
H
Even
Odd
L
L
X
X
Even
NA = not applicable, NC = no change, X = don’t care
† Summation of high-level inputs includes PARITY along with Bi inputs.
‡ Output states shown assume the ERR output was previously high.
§ In this mode, the ERR output, when enabled, shows inverted parity of the A bus.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
OEA
ERR
CLR
GND
FUNCTION TABLE
OUTPUT AND I/O
Bi †
ERR ‡
A
B
PARITY
of L’s
H
NA
NA
A
NA
L
Odd
H
B
NA
NA
Even
L
X
X
NA
NA
H
NC
H
X
Z
Z
Z
L
H
L
NA
NA
A
NA
H
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN74BCT29834
DW OR NT PACKAGE
(TOP VIEW)
V
1
24
CC
A1
B1
2
23
A2
B2
3
22
A3
B3
4
21
A4
B4
5
20
A5
B5
6
19
A6
B6
7
18
A7
B7
8
17
A8
B8
9
16
PARITY
10
15
OEB
11
14
CLK
12
13
FUNCTION
A data to B bus and generate parity
B data to A bus and check parity
Clear error-flag register
Isolation §
A data to B bus and generate inverted
parity
Copyright
1993, Texas Instruments Incorporated
2–1

SN74BCT29834NT Summary of contents