SAB-C167CR-LM

Manufacturer Part NumberSAB-C167CR-LM
Description16-bit microcontroller with 2x2 KByte RAM
ManufacturerInfineon Technologies AG
SAB-C167CR-LM datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 35/74:

Parallel Ports

Download datasheet (2Mb)Embed
PrevNext
C167CR
C167SR
Parallel Ports
The C167CR provides up to 111 I/O lines which are organized into eight input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
The input threshold of Port 2, Port 3, Port 7, and Port 8 is selectable (TTL or CMOS like),
where the special CMOS like input threshold reduces noise sensitivity due to the input
hysteresis. The input threshold may be selected individually for each byte of the
respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port 2, Port 8 and Port 7 (and parts of PORT1) are associated with the capture inputs or
compare outputs of the CAPCOM units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE/WRH, and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
The edge characteristics (transition time) of the C167CR’s port drivers can be selected
via the Port Driver Control Register (PDCR). Two bits select fast edges (‘0’) or reduced
edges (‘1’) for bus interface pins and non-bus pins separately.
PDCR.0 = BIPEC controls PORT0, PORT1, Port 4, RD, WR, ALE, CLKOUT, BHE/WRH.
PDCR.4 = NBPEC controls Port 3, Port 8, RSTOUT, RSTIN (bidir. reset mode).
Data Sheet
31
V3.2, 2001-07