SAB-C167CR-LM

Manufacturer Part NumberSAB-C167CR-LM
Description16-bit microcontroller with 2x2 KByte RAM
ManufacturerInfineon Technologies AG
SAB-C167CR-LM datasheet
 


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Page 54/74:

Clock Generation Modes

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Table 10
C167CR Clock Generation Modes
CLKCFG
CPU Frequency
f
f
(P0H.7-5)
=
CPU
OSC
× 4
f
1 1 1
OSC
× 3
f
1 1 0
OSC
× 2
f
1 0 1
OSC
× 5
f
1 0 0
OSC
× 1
f
0 1 1
OSC
× 1.5
f
0 1 0
OSC
f
0 0 1
/ 2
OSC
× 2.5
f
0 0 0
OSC
1)
The external clock input range refers to a CPU clock range of 10 … 33 MHz (PLL operation).
2)
The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001
the internal oscillator (input clock signal) by a 2:1 prescaler.
f
The frequency of
is half the frequency of
CPU
the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
× F). With every F’th transition of
f
f
=
CPU
OSC
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
f
it is locked to
. The slight variation causes a jitter of
OSC
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
Data Sheet
External Clock
1)
× F
Input Range
2.5 to 8.25 MHz
3.33 to 11 MHz
5 to 16.5 MHz
2 to 6.6 MHz
1 to 33 MHz
6.66 to 22 MHz
2 to 66 MHz
4 to 13.2 MHz
f
and the high and low time of
OSC
f
for any TCL.
OSC
Table
f
the PLL circuit synchronizes the CPU
OSC
50
Notes
Default configuration
2)
Direct drive
CPU clock via prescaler
) the CPU clock is derived from
B
f
OSC
10). The PLL multiplies the input
f
is constantly adjusted so
CPU
f
which also effects the
CPU
V3.2, 2001-07
C167CR
C167SR
f
(i.e.
CPU
.