SAB-C167CR-LM

Manufacturer Part NumberSAB-C167CR-LM
Description16-bit microcontroller with 2x2 KByte RAM
ManufacturerInfineon Technologies AG
SAB-C167CR-LM datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 58/74:

A/D Converter Characteristics

Download datasheet (2Mb)Embed
PrevNext

A/D Converter Characteristics

(Operating Conditions apply)
Table 12

A/D Converter Characteristics

Parameter
Analog reference supply
Analog reference ground
Analog input voltage range
Basic clock frequency
Conversion time
Calibration time after reset
Total unadjusted error
Internal resistance of
reference voltage source
Internal resistance of
analog source
ADC input capacitance
1)
V
TUE is tested at
= 5.0 V,
AREF
within the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
+ 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.
V
V
(i.e.
=
AREF
DD
The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±4 LSB.
2)
V
may exceed
V
or
AIN
AGND
these cases will be X000
or X3FF
H
3)
f
The limit values for
must not be exceeded when selecting the CPU frequency and the ADCTC setting.
BC
4)
This parameter includes the sample time
result register with the conversion result.
t
Values for the basic clock
BC
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5)
During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.
6)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
Symbol
Limit Values
min.
V
SR
4.0
AREF
V
V
SR
- 0.1
AGND
SS
V
V
SR
AIN
AGND
f
0.5
BC
t
CC
C
t
CC
CAL
TUE
CC
R
SR
AREF
R
SR
ASRC
C
CC
AIN
V
V
= 0 V,
= 4.9 V. It is guaranteed by design for all other voltages
AGND
DD
V
up to the absolute maximum ratings. However, the conversion result in
AREF
, respectively.
H
t
, the time for determining the digital result and the time to load the
S
depend on programming and can be taken from
54
C167CR
C167SR
Unit Test
Condition
max.
1)
V
+ 0.1 V
DD
V
+ 0.2
V
SS
2)
V
V
AREF
3)
6.25
MHz
4)
t
t
40
+
BC
S
t
t
+ 2
= 1/
CPU
CPU
5)
t
3328
BC
1)
± 2
LSB
k Ω
t
t
/ 60
in [ns]
BC
BC
- 0.25
k Ω
t
t
/ 450
in [ns]
S
S
- 0.25
7)
33
pF
Table
13.
V3.2, 2001-07
f
CPU
6)7)
7)8)
I
OV