MC14560BCP

Manufacturer Part NumberMC14560BCP
ManufacturerFreescale Semiconductor, Inc
MC14560BCP datasheet
 
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
Page 5/13:

INTRODUCTION

Download datasheet (308Kb)Embed
PrevNext

INTRODUCTION

Frequently in small digital systems, simple decimal arith-
metic is performed. Decimal data enters and leaves the sys-
tem arithmetic unit in a binary coded decimal (BCD) format.
The adder/subtracter in the arithmetic unit may be required
to accept sign as well as magnitude, and generate sign,
magnitude, and overflow. In the past, it has been cumber-
some to build sign and magnitude adder/subtracters. Now,
using Motorola’s MSI CMOS functions, the MC14560 NBCD
Adders and MC14561 9’s Complementers, NBCD adder/
subtracters may be built economically, with surprisingly low
package count and moderate speed.
Some background information on BCD arithmetic is pres-
ented here, followed by simple circuits for unsigned adder/
subtracters. The final circuit discussed is an adder/subtracter
for signed numbers with complete overflow and sign correc-
tion logic.
DECIMAL NUMBER REPRESENTATION
Because logic elements are binary or two–state devices,
decimal digits are generally represented as a group of bits in
a weighted format. There are many possible binary codes
which can be used to represent a decimal number. One of
the most popular codes using 4 binary digits to represent 0
thru 9 is Natural Binary Coded Decimal (NBCD or 8–4–2–1
code).
NBCD is a weighted code. If a value of “0” or “1” is as-
signed to each of the bit positions, where the rightmost posi-
tion is 2 0 and the leftmost is 2 3 , and the values are summed
for a given code, the result is equal to the decimal digit repre-
@
sented by the code. Thus, 0110 equals 0
@
2 0 = 4 + 2 = 6. The 1010, 1011, 1100, 1101, 1110, and 1111
0
binary codes are not used. Because of these illegal states,
the addition and subtraction of NBCD numbers is more com-
plex than similar calculations on straight binary numbers.
ADDITION OF UNSIGNED NBCD NUMBERS
When 2 NBCD digits, A and B, and a possible carry, C, are
added, a total of 20 digit sums (A + B + C) are possible as
shown in Table 1.
The binary representations for the digit sums 10 thru 19
are offset by 6, the number of unused binary states, and are
not correct. An algorithm for obtaining the correct sum is
shown in Figure 1. A conventional method of implementing
the BCD addition algorithm is shown in Figure 2(a). The
NBCD digits, A and B, are summed by a 4 bit binary full ad-
der. The resultant (sum and carry) is input to a binary/BCD
code converter which generates the correct BCD code and
carry.
An NBCD adder block which performs the above function
is available in a single CMOS package (MC14560).
MOTOROLA CMOS LOGIC DATA
APPLICATIONS INFORMATION
Figure 2(b) shows n decades cascaded for addition of n digit
unsigned NBCD numbers. Add time is typically 0.1 + 0.2n s
for n decades. When the carry out of the most significant de-
cade is a logical “1”, an overflow is indicated.
COMPLEMENT ARITHMETIC
Complement arithmetic is used in NBCD subtraction. That
is, the “complement” of the subtrahend is added to the minu-
end. The complementing process amounts to biasing the
subtrahend such that all possible sums are positive. Consid-
er the subtraction of the NBCD numbers, A and B:
where R is the result. Now bias both sides of the equation
by 10 N – 1 where N is the number of digits in A and B.
Rearranging,
R + 10 N – 1 A + (10 N – 1 – B)
The term (10 N – 1 – B), – B biased by 10 N – 1, is known as
the 9’s complement of B. When A > B, R + 10 N – 1 > 10 N – 1;
thus R is a positive number. To obtain R, 1 is added to R +
10 N – 1, and the carry term, 10 N , is dropped. The addition of
1 is called End Around Carry (EAC).
When A < B, R + 10 N – 1 < 10 N – 1, no EAC results and R
is a negative number biased by 10 N – 1; thus R + 10 N – 1 is
the 9’s complement of R.
SUBTRACTION OF UNSIGNED NBCD NUMBERS
Nine’s complement arithmetic requires an element to per-
form the complementing function. An NBCD 9’s comple-
@
@
menter may be implemented using a 4 bit binary adder and 4
2 3 + 1
2 2 + 1
2 1 +
inverters, or with combinatorial logic. The Motorola MC14561
9’s complementer is available in a single package. It has true
and inverted complement disable, which allow straight–
through or complement modes of operation. A “zero” line
forces the output to “0”. Figure 3 shows an NBCD subtracter
block using the MC14560 and MC14561. Also shown are n
cascaded blocks for subtraction of n digit unsigned numbers.
Subtract time is 0.6 + 0.4n s for n stages. Underflow (bor-
row) is indicated by a logical “0” on the carry output of the
most significant digit. A “0” carry also indicates that the differ-
ence is a negative number in 9’s complement form. If the re-
sult is input to a 9’s complementer, as shown, and its mode
controlled by the carry out of the most significant digit, the
output of the complementer will be the correct negative mag-
nitude. Note that the carry out of the most significant digit
(MSD) is the input to carry in of the least significant digit
(LSD). This End Around Carry is required because subtrac-
tion is done in 9’s complement arithmetic.
By controlling the complement and overflow logic with an
add/subtract line, both addition and subtraction are per-
formed using the basic subtracter blocks (Figure 4).
R = A – B
R + 10 N – 1 A – B + 10 N – 1
MC14560B
5