MC14560BCP

Manufacturer Part NumberMC14560BCP
ManufacturerFreescale Semiconductor, Inc
MC14560BCP datasheet
 


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Table 1. Sum = A + B + C
Decimal
Binary Sums
Numbers
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
10
1011
11
1100
Non valid
12
1101
BCD
13
1110
representation
14
1111
15
0000 + Carry
16
0001 + Carry
17
0010 + Carry
18
0011 + Carry
19
THOUSANDS
6,941
+
5,870
4 BIT BINARY ADDERS
DIGIT BINARY SUMS
BINARY SUMS WITH
CARRY FROM CONVERTERS
CODE CONVERTERS
C out
CORRECTED SUM
12,811
1
Figure 4. Unsigned NBCD Addition Algorithm
A
B
4 BIT BINARY FULL ADDER
C in
BINARY TO NBCD
C out
CODE CONVERTER
RESULT, R
(a) MC14560 Block Diagram
Figure 5. Addition of Unsigned NBCD Numbers
MC14560B
6
ADDITION AND SUBTRACTION OF SIGNED NBCD
NUMBERS
Corrected
Binary Sums
Using MC14560 NBCD Adders and MC14561 9’s Comple-
0000
menters, a sign and magnitude adder/subtracter can be con-
0001
figured (Figure 5). Inputs A and B are signed positive (A S , B S
0010
= “0”) or negative (A S , B S = “1”). B is added to or subtracted
0011
from A under control of an Add/Sub line (subtraction = “1”).
0100
The result, R, of the operation is positive signed, positive
0101
0110
signed with overflow, negative signed, or negative signed
0111
with overflow. Add/subtract time is typically 0.6 + 0.4n s for
1000
n decades.
1001
An exclusive–OR of Add/Sub line and B S produces B ,
0000 + Carry
which controls the B complementers. If B S , the sign of B, is a
0001 + Carry
logical “1” (B is negative) and the Add/Sub line is a “0” (add
0010 + Carry
B to A), then the output of the exclusive–OR (B S ) is a logical
0011 + Carry
“1” and B is complemented. If B S = “1” and Add/Sub = “1”, B
0100 + Carry
is not complemented since subtracting a negative number is
0101 + Carry
the same as adding a positive number. When Add/Sub is a
0110 + Carry
0111 + Carry
“1” and B S = “0”, B S is a “1” and B is complemented. The A
1000 + Carry
complementer is controlled by the A sign bit, A S . When A S =
1001 + Carry
“1”, A is complemented.
HUNDREDS
0110
1001
0101
1000
ADDER
ADDER
1
1
C in
C in
1011
1
0001
1100
0010
1
C out
C out
0 0 1 0
1 0 0 0
A1
B1
A2
C in
C out
C in
MC14560
MC14560
R1
R2
Typical Add Time = 0.1 + 0.2n s
where n = Number of Decades
(b) n–Decade Adder
TENS
UNITS
0100
0001
0111
0000
ADDER
ADDER
0
C in
1011
0001
1011
0001
C out
0 0 0 1
0 0 0 1
B2
A n
B n
C out
C in
C out
MC14560
OVERFLOW
R n
MOTOROLA CMOS LOGIC DATA