GAL6002B-20LP Lattice Semiconductor Corp., GAL6002B-20LP Datasheet

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GAL6002B-20LP

Manufacturer Part Number
GAL6002B-20LP
Description
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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• HIGH PERFORMANCE E
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
• E
• UNPRECEDENTED FUNCTIONAL DENSITY
• HIGH-LEVEL DESIGN FLEXIBILITY
• APPLICATIONS INCLUDE:
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6002_02
Features
Description
— 15ns Maximum Propagation Delay
— 75MHz Maximum Frequency
— 6.5ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS
— 90mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
2
CELL TECHNOLOGY
and FPLA Devices
®
Advanced CMOS Technology
2
CMOS
®
TECHNOLOGY
2
CMOS technology offers
®
1
Functional Block Diagram
Macrocell Names
PinNames
Pin Configuration
ILMC
IOLMC I/O LOGIC MACROCELL
BLMC
OLMC
I
ICLK
OCLK
INPUTS
0
2-11
CLOCK
- I
INPUT
NC
10
I
I
I
I
I
I
{
11
5
7
9
12
4
INPUT LOGIC MACROCELL
BURIED LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
INPUT
INPUT CLOCK
OUTPUT CLOCK
2
GAL6002
11
Top View
ILMC
0
14
PLCC
2
7
BLMC
High Performance E
ICLK
28
16
D
E
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
AND
OR
Generic Array Logic™
I/O/Q
V
GND
CC
GAL6002
D
E
OUTPUT
ENABLE
14
I/ICLK
BIDIRECTIONAL
POWER (+5V)
GROUND
GND
23
OLMC
I
I
I
I
I
I
I
I
I
I
2
OCLK
CMOS FPLA
1
12
6
6002
GAL
DIP
14
23
IOLMC
July 1997
18
24
13
{
OUTPUTS
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK
OUTPUT
14 - 23
CLOCK

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GAL6002B-20LP Summary of contents

Page 1

... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 2

... GAL6002 Commercial Device Ordering Information Commercial Grade Specifications Part Number Description GAL6002B Device Name Speed (ns Low Power Power XXXXXXXX Specifications GAL6002 Grade Blank = Commercial Package P = Plastic DIP J = PLCC ...

Page 3

Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC) The GAL6002 features two configurable input sections. The ILMC section corresponds to the dedicated input pins (2-11) and the IOLMC to the I/O pins (14-23). Each input section is individually configurable ...

Page 4

ILMC and IOLMC Configurations INPUT or I/O Input Macrocell JEDEC Fuse Numbers INSYNC INLATCH ILMC 8218 8219 0 8220 8221 1 8222 8223 2 8224 8225 3 8226 8227 4 8228 8229 5 8230 8231 6 8232 8233 7 8234 ...

Page 5

OLMC and BLMC Configurations OLMC ONLY XORD(i) D Vcc XORE(i) E CKS(i) OLMC JEDEC Fuse Numbers OLMC CKS OUTSYNC 0 8178 8179 1 8182 8183 2 8186 8187 3 8190 8191 4 8194 8195 5 8198 8199 6 8202 8203 ...

Page 6

Logic Diagram Specifications GAL6002 6 ...

Page 7

Logic Diagram (Continued) Specifications GAL6002 7 ...

Page 8

Absolute Maximum Ratings Supply voltage V ...................................... –0.5 to +7V CC Input voltage applied .......................... –2 Off-state output voltage applied ......... –2 Storage Temperature ................................ –65 to 150 C Ambient Temperature with Power Applied ........................................ –55 ...

Page 9

AC Switching Characteristics TEST DESCRIPTION PARAM. COND pd1 A Combinatorial Input to Combinatorial Output t pd2 A Feedback or I/O to Combinational Output t pd3 A Transparent Latch Input to Combinatorial Output t co1 A Input Latch ...

Page 10

AC Switching Characteristics (Continued) TEST DESCRIPTION PARAMETER COND wl1 — ICLK Pulse Duration, Low t wl2 — OCLK Pulse Duration, Low t wl3 — STCLK Pulse Duration, Low t arw — Reset Pulse Duration ...

Page 11

Switching Waveforms INPUT or I/O FEEDBACK COMBINATORIAL OUTPUT Combinatorial Output INPUT or VALID INPUT I/O FEEDBACK t t su1 ICLK (LATCH) t pd3 COMBINATORIAL OUTPUT Latched Input INPUT or VALID INPUT I/O FEEDBACK t su4 Sum Term CLK REGISTERED OUTPUT ...

Page 12

Descriptions CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC REGISTER ARRAY f max with No Feedback Note: fmax with no feedback ...

Page 13

Array Description 2 The GAL6002 contains two E reprogrammable arrays. The first is an AND array and the second array. These arrays are de- scribed in detail below. AND ARRAY The AND array is organized as 78 ...

Page 14

Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL6002 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr ...

Page 15

Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 ...

Page 16

Typical AC and DC Characteristic Diagrams Vol vs Iol 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 Supply Voltage (V) Delta Icc vs ...

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