CP80C86-2 Intersil Corporation, CP80C86-2 Datasheet

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CP80C86-2

Manufacturer Part Number
CP80C86-2
Description
CMOS 16-Bit Microprocessor
Manufacturer
Intersil Corporation
Datasheet
March 1997
Features
• Compatible with NMOS 8086
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 A Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
- Multiply and Divide
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0
- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
http://www.intersil.com or 407-727-9207
Copyright
Description
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, minimum for
small systems and maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
exception of CLOCK) and industry standard operation allow
use of existing NMOS 8086 hardware and software designs.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
o
o
C to +70
C
o
o
C to +85
C
-55
o
o
C to +125
C
SMD#
-55
CLCC
-55
SMD#
-55
©
Intersil Corporation 1999
3-141
80C86
CMOS 16-Bit Microprocessor
TEMP. RANGE
5MHz
8MHz
o
o
0
C to +70
C
CP80C86
CP80C86-2 E40.6
o
o
-40
C to +85
C lP80C86
IP80C86-2
o
o
0
C to +70
C
CS80C86
CS80C86-2 N44.65
o
o
-40
C to +85
C lS80C86
IS80C86-2
o
o
0
C to +70
C
CD80C86
CD80C86-2 F40.6
o
o
-40
C to +85
C ID80C86
ID80C86-2
o
o
C to +125
C MD80C86/B MD80C86-
2/B
o
o
C to +125
C 8405201QA 8405202QA F40.6
o
o
C to +125
C MR80C86/B MR80C86-
2/B
o
o
C to +125
C 8405201XA 8405202XA J44.A
File Number
PKG.
NO.
E40.6
N44.65
F40.6
F40.6
J44.A
2957.1

Related parts for CP80C86-2

CP80C86-2 Summary of contents

Page 1

... PLCC CERDIP + + +125 C SMD# -55 CLCC -55 SMD# -55 © Intersil Corporation 1999 3-141 80C86 CMOS 16-Bit Microprocessor TEMP. RANGE 5MHz 8MHz +70 C CP80C86 CP80C86-2 E40 - +85 C lP80C86 IP80C86 +70 C CS80C86 CS80C86-2 N44. - +85 C lS80C86 IS80C86 +70 C CD80C86 CD80C86-2 F40 - +85 C ID80C86 ID80C86 ...

Page 2

Pinouts MAX MODE 80C86 MIN MODE 80C86 AD10 AD10 AD9 AD9 AD8 AD8 AD7 AD7 AD6 AD6 AD5 AD5 AD4 AD4 AD3 AD3 AD2 AD2 AD1 AD1 AD0 AD0 80C86 80C86 80C86 (DIP) TOP VIEW MAX GND ...

Page 3

Functional Diagram EXECUTION UNIT REGISTER FILE DATA POINTER AND INDEX REGS (8 WORDS) 16-BIT ALU FLAGS TEST INTR NMI RQ/GT0 HOLD HLDA CLK MEMORY INTERFACE BUS INTERFACE UNIT EXECUTION UNIT 80C86 BUS INTERFACE UNIT RELOCATION REGISTER FILE SEGMENT ...

Page 4

Pin Description The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers). PIN ...

Page 5

Pin Description (Continued) The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers). ...

Page 6

Minimum Mode System (Continued) The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/ minimum mode are described; all other pin functions are as described below. PIN SYMBOL NUMBER TYPE DT DEN ...

Page 7

Maximum Mode System (Continued) The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique to maximum mode are described below. PIN SYMBOL NUMBER TYPE RQ/GT0 31, ...

Page 8

Functional Description Static Operation All 80C86 circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microproces- sors. The ...

Page 9

Except for the performance penalty, this double access is transpar- ent to the software. The performance penalty does ...

Page 10

Status bits S3 through S7 are time multiplexed with high order address bits and the BHE signal, and are therefore valid during T2 through T4. S3 and S4 indicate which seg- ment register (see Instruction Set Description) was used for ...

Page 11

NWAIT) = TCY T1 T2 CLK ALE S2-S0 BHE, ADDR/ A19-A16 STATUS BUS RESERVED A15-A0 ADDR/DATA RD, INTA READY WAIT DT/R DEN MEMORY ACCESS TIME WR 80C86 T3 TWAIT BHE S7-S3 A19-A16 FOR DATA IN ...

Page 12

External Interface Processor RESET and Initialization Processor initialization or start up is accomplished with activa- tion (HIGH) of the RESET pin. The 80C86 RESET is required to be HIGH for greater than 4 CLK cycles. The 80C86 will termi- nate ...

Page 13

During the response sequence (Figure 5) the processor exe- cutes two successive (back-to-back) interrupt acknowledge cycles. The 80C86 emits the LOCK signal (Max mode only) from T2 of the first bus cycle until T2 of the second. A local bus ...

Page 14

The read control signal is also asserted at T2. The read (RD) signal causes the addressed device to enable its data bus drivers to the local bus. Some time later, valid data will be available on the bus and ...

Page 15

V CC MN/MX M/IO 82C8A/85 INTA CLK CLOCK RD GENERATOR READY WR RES RESET RDY DT/R DEN WAIT ALE GND STATE GENERATOR 80C86 CPU GND AD0-AD15 1 A16-A19 BHE GND ...

Page 16

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 17

AC Electrical Specifications MINIMUM COMPLEXITY SYSTEM SYMBOL PARAMETER TIMING REQUIREMENTS (1) TCLCL Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TCH1CH2 CLK Rise Time (5) TCL2C1 CLK ...

Page 18

AC Electrical Specifications MINIMUM COMPLEXITY SYSTEM SYMBOL PARAMETER (25) TLLAX Address Hold Time to ALE Inactive (26) TCLDV Data Valid Delay (27) TCLDX2 Data Hold Time (28) TWHDX Data Hold Time After ...

Page 19

Waveforms CLK (82C84A OUTPUT) (30) TCHCTV M/IO (17) TCLAV BHE/S7, A19/S6-A16/S3 (23) TCLLH ALE RDY (82C84A INPUT) SEE NOTE READY (80C86 INPUT) AD15-AD0 RD READ CYCLE (WR, INTA = DT/R DEN FIGURE 7A. BUS TIMING - MINIMUM ...

Page 20

Waveforms (Continued) CLK (82C84A OUTPUT) (17) TCLAV AD15-AD0 WRITE CYCLE DEN (RD, INTA, DT (19) TCLAZ AD15-AD0 DT/R INTA CYCLE (SEE NOTE) (RD INTA BHE = DEN SOFTWARE ...

Page 21

AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) TIMING REQUIREMENTS SYMBOL PARAMETER (1) TCLCL CLK Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TCH1CH2 CLK ...

Page 22

AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) TIMING REQUIREMENTS SYMBOL PARAMETER (23) TCLAV Address Valid Delay (24) TCLAX Address Hold Time (25) TCLAZ Address Float Delay (26) TCHSZ Status ...

Page 23

AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) TIMING REQUIREMENTS SYMBOL PARAMETER (35) TCVNV Control Active Delay (Note 10) (36) TCVNX Control Inactive Delay (Note 10) (37) TAZRL Address Float ...

Page 24

Waveforms CLK TCLAV QS0, QS1 (21) TCHSV S2, S1, S0 (EXCEPT HALT) (23) TCLAV BHE/S7, A19/S6-A16/S3 TSVLH (27) TCLLH ALE (82C88 OUTPUT) NOTE RDY (82C84 INPUT) READY 80C86 INPUT) READ CYCLE TCLAV AD15-AD0 RD (41) TCHDTL DT/R 82C88 OUTPUTS MRDC ...

Page 25

Waveforms (Continued) CLK TCHSV (21) S2, S1, S0 (EXCEPT HALT) WRITE CYCLE AD - DEN 82C88 OUTPUTS SEE NOTES AMWC OR AIOWC 18, 19 MWTC OR IOWC INTA CYCLE AD15-AD0 (SEE NOTES 21, 22) (25) TCLAZ AD15-AD0 (28) ...

Page 26

Waveforms (Continued) CLK TCLGH (44) (1) TCLCL RQ/GT PREVIOUS GRANT AD15-AD0 RD, LOCK BHE/S7, A19/S0-A16/S3 S2, S1, S0 NOTE: The coprocessor may not drive the busses outside the region shown without risking contention. FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ...

Page 27

Waveforms (Continued) AC Test Circuit OUTPUT FROM DEVICE UNDER TEST NOTE: Includes stay and jig capacitance. AC Testing Input, Output Waveform INPUT NOTE: AC Testing: All input signals (other than ...

Page 28

Burn-In Circuits GND RIO GND RIO V CL RIO GND RIO GND RIO V CL RIO GND RIO GND RIO GND RIO V CL RIO V CL RIO V CL OPEN OPEN OPEN OPEN GND GND GND ...

Page 29

Burn-In Circuits (Continued) RIO RIO RIO RIO RIO RIO RIO GND NOTES 5.5V 0.5V, GND = 0V. CC Input voltage limits (except clock): V (maximum (minimum) = 2.6V, V (clock -0.4V) minimum. ...

Page 30

Metallization Topology DIE DIMENSIONS: 249.2 x 290 METALLIZATION: Type: Silicon - Aluminum Å Å Thickness: 11k 2k Metallization Mask Layout AD11 AD12 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK 80C86 GLASSIVATION: ...

Page 31

Instruction Set Summary MNEMONIC AND DESCRIPTION DATA TRANSFER MOV = MOVE: Register/Memory to/from Register Immediate to Register/Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register/Memory to Segment Register †† Segment Register to Register/Memory PUSH = Push: Register/Memory Register ...

Page 32

Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Immediate to Register/Memory Immediate to Accumulator INC = Increment: Register/Memory Register AAA = ASCll Adjust for Add DAA = Decimal Adjust for Add SUB = Subtract: Register/Memory and Register to Either Immediate from ...

Page 33

Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION RCR = Rotate Through Carry Right AND = And: Reg./Memory and Register to Either Immediate to Register/Memory Immediate to Accumulator TEST = And Function to Flags, No Result: Register/Memory and Register Immediate Data ...

Page 34

Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Intersegment Intersegment Adding Immediate to SP JE/JZ = Jump on Equal/Zero JL/JNGE = Jump on Less/Not Greater or Equal JLE/JNG = Jump on Less or Equal/ Not Greater JB/JNAE = Jump on Below/Not ...

Page 35

Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION NOTES 8-bit accumulator AX = 16-bit accumulator CX = Count register DS= Data segment ES = Extra segment Above/below refers to unsigned value. Greater = more positive; Less = less positive ...

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