LM49352RLX/NOPB National Semiconductor, LM49352RLX/NOPB Datasheet

IC AMP AUDIO MONO D1.4W 36USMD

LM49352RLX/NOPB

Manufacturer Part Number
LM49352RLX/NOPB
Description
IC AMP AUDIO MONO D1.4W 36USMD
Manufacturer
National Semiconductor
Series
Boomer®, PowerWise®r
Type
Class Dr
Datasheet

Specifications of LM49352RLX/NOPB

Output Type
1-Channel (Mono) with Mono and Stereo Headphones
Max Output Power X Channels @ Load
1.4W x 1 @ 8 Ohm; 65mW x 2 @ 32 Ohm
Features
Depop, Differential Inputs, I²C, I²S, Microphone, Shutdown, Volume Control
Mounting Type
Surface Mount
Package / Case
36-MicroSMDxt
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Other names
LM49352RLX

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM49352RLX/NOPB
Manufacturer:
CYPRESS
Quantity:
562
© 2010 National Semiconductor Corporation
Mono Class D Audio Codec Subsystem with Ground
Referenced Headphone Amplifiers, Earpiece Driver, and
Audio DSP
1.0 General Description
The LM49352 is a high performance mixed signal audio sub-
system. The LM49352 includes a high quality stereo DAC, a
high quality stereo ADC, a stereo headphone amplifier, which
supports True Ground operation, a low EMI Class D loud-
speaker amplifier, and an earpiece speaker amplifier. It com-
bines advanced audio processing, conversion, mixing, and
amplification in the smallest possible footprint while extending
the battery life of feature rich portable devices.
The LM49352 features dual bi-directional I
interfaces and an I
stereo DAC path features an SNR of 103dB with 24-bit 48 kHz
input. The headphone amplifier delivers 65mW
32Ω single-ended stereo load with less than 1% distortion
(THD+N) when HP_V
delivers up to 970mW into an 8Ω load with less than 1% dis-
tortion when LS_V
The LM49352 employs advanced techniques to extend bat-
tery life, to reduce controller overhead, to speed development
time, and to eliminate click and pop artifacts. Boomer audio
power amplifiers are designed specifically for mobile devices
and require minimal PCB area and external components.
2.0 Applications
3.0 Key Specifications
Boomer® is a registered trademark of National Semiconductor Corporation.
Smart Phones
Mobile Phones and VOIP Phones
Portable GPS Navigator and Portable Gaming Devices
Portable DVD/CD/AAC/MP3/MP4 Players
Digital Cameras/Camcorders
Class D Amplifier Efficiency
P
P
1% THD
P
P
P
EP
HP
LS
LS
LS
at LS_V
at LS_V
at LS_V
at A_V
at HP_V
DD
DD
DD
DD
DD
= 3.3V, 32Ω, 1% THD
= 5V, 8Ω, 1% THD
= 4.2V, 8Ω, 1% THD
= 3.3V, 8Ω, 1% THD
DD
= 2.8V, Stereo 32Ω,
2
C compatible interface for control. The
= 4.2V.
DD
= 2.8V. The loudspeaker amplifier
300727
2
S or PCM audio
65mW/ch (typ)
RMS
970mW (typ)
590mW (typ)
58mW (typ)
1.4W (typ)
93% (typ)
(typ) to a
LM49352
4.0 Features
SNR (Stereo DAC at 48kHz)
PSRR at 217 Hz, A_V
AUX)
Ultra efficient, spread spectrum Class D loudspeaker
amplifier that operates at 93% efficiency
Low voltage, true ground headphone amplifier operation
High performance 103dB SNR stereo DAC
High performance 97dB SNR stereo ADC
Up to 96kHz stereo audio playback
Up to 48kHz stereo recording
Dual bidirectional I
Read/write I
Flexible digital mixer with sample rate conversion
Sigma-delta PLL clock network that supports system
clocks up to 50MHz including 13MHz, 19.2MHz, and
26MHz
Dual stereo 5 band parametric equalizers
Cascadable DSP effects that allow stereo 10 band
parametric equalization
ALC/Limiter/Compressor on both DAC and ADC paths
Dedicated Earpiece Speaker Amplifier
Stereo auxiliary inputs and mono differential input
Differential microphone input with single-ended option
Automatic level control for digital audio inputs, mono
differential input, microphone input, and stereo auxiliary
inputs
Flexible audio routing from input to output
16 Step volume control for microphone with 2dB steps
32 Step volume control for auxiliary inputs in 1.5dB steps
4 Step volume control for class D loudspeaker amplifier
8 Step volume control for headphone amplifier
Micro-power shutdown mode
Available in the 3.3 x 3.3 mm 36 bump micro SMD package
2
C compatible control interface
2
S or PCM compatible audio interfaces
DD
= 3.3V, (HP from
June 30, 2010
www.national.com
103dB (typ)
100dB (typ)

Related parts for LM49352RLX/NOPB

LM49352RLX/NOPB Summary of contents

Page 1

... LS_V = 4.2V, 8Ω, 1% THD LS DD ■ LS_V = 3.3V, 8Ω, 1% THD LS DD Boomer® registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation LM49352 ■ SNR (Stereo DAC at 48kHz) ■ PSRR at 217 Hz, A_V AUX) 4.0 Features ■ Ultra efficient, spread spectrum Class D loudspeaker amplifier that operates at 93% efficiency ■ ...

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LM49352 Overview www.national.com FIGURE 1. LM49352 Block Diagram 2 30072777 ...

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Typical Application FIGURE 2. Example Application in Multimedia Phone with Dedicated Earpiece Speaker and Mono Loudspeaker 3 30072785 www.national.com ...

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FIGURE 3. Example Application in Multimedia Phone Using Multiple Media Sources www.national.com 4 30072786 ...

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FIGURE 4. Example Application in a Multimedia Phone with Stereo Loudspeaker 5 30072787 www.national.com ...

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FIGURE 5. Example Application in a Portable Media Player with Stereo Loudspeakers www.national.com 6 30072788 ...

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General Description ......................................................................................................................... 1 2.0 Applications .................................................................................................................................... 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Features ........................................................................................................................................ 1 5.0 LM49352 Overview .......................................................................................................................... 2 6.0 Typical Application ........................................................................................................................... 3 7.0 Connection Diagrams ..................................................................................................................... 10 7.1 PIN TYPE DEFINITIONS ........................................................................................................ 12 8.0 ...

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FIGURE 27. Demo Board Schematic .......................................................................................................... 104 FIGURE 28. Top Silkscreen ..................................................................................................................... 105 FIGURE 29. Top Layer ........................................................................................................................... 105 FIGURE 30. Inner Layer 2 ....................................................................................................................... 106 FIGURE 31. Inner Layer 3 ....................................................................................................................... 106 FIGURE 32. Bottom Layer ...................................................................................................................... 107 FIGURE ...

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TABLE 60. EQ_BAND_5 (0x8Fh) ................................................................................................................ 81 TABLE 61. SOFTCLIP1 (0x90h) ................................................................................................................. 84 TABLE 62. SOFTCLIP2 (0x91h) ................................................................................................................. 85 TABLE 63. SOFTCLIP3 (0x92h) ................................................................................................................. 86 TABLE 64. DAC_ALC_1 (0xA0h) ................................................................................................................ 87 TABLE 65. DAC_ALC_2 (0xA1h) ................................................................................................................ 87 TABLE 66. DAC_ALC_3 (0xA2h) ...

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Connection Diagrams 36 Bump micro SMD Order Number LM49352RL See NS Package Number RLA36MMA Order Number Package 36 Bump micro LM49352RL SMDxt 36 Bump micro LM49352RLX SMDxt www.national.com 30072711 LM49352RL Pinout Diagram Top View (Bump Side Down) Ordering Information ...

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Pin Descriptions Pin Pin Name Type A1 HPR Analog A2 A_V Supply DD A3 AGND Supply A4 DAC REF Analog A5 ADC REF Analog A6 SDA Digital B1 HPL Analog B2 AUX_R/AUX+ Analog B3 AUX_L/AUX- Analog B4 PORT2_SYNC Digital B5 ...

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PIN TYPE DEFINITIONS Analog Input — A pin that is used by the analog and is never driven by the device. Sup- plies are part of this classification. Analog Output — A pin that is driven by the device ...

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... Absolute Maximum Ratings 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage (A_V and LS_V ) DD DD Digital Supply Voltage D_V DD I/O Supply Voltage I/O_V DD Headphone Supply Voltage ...

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Symbol Parameter Analog Supply Current (MP3 Mode) Analog Supply Current (FM Mode Analog Supply Current (FM Record Mode) Analog Supply Current (CODEC Mode) PLLI PLL Total Active Current DD HPI Headphone Quiescent Current DD LSI Loudspeaker Quiescent Current ...

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Symbol Parameter P Output Power O PSRR Power Supply Rejection Ratio SNR Signal-to-Noise Ratio e OS Output Noise V Offset Voltage OS HEADPHONE AMPLIFIERS THD+N Total Harmonic Distortion + Noise P Headphone Output Power O Conditions = 8Ω ...

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Symbol Parameter PSRR Power Supply Rejection Ratio SNR Signal to Noise Ratio e Output Noise OS X Crosstalk TALK ΔA Channel-to-Channel Gain Matching CH-CH V Output Offset Voltage OS AUXILIARY OUTPUT/EARPIECE AMPLIFIER THD+N Total Harmonic Distortion P Output Power OUT ...

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Symbol Parameter V Output Offset Voltage OS T Turn-On time WU STEREO ADC ADC Total Harmonic Distortion + THD+N ADC Noise PB ADC Passband ADC R ADC Ripple ADC SNR ADC Signal to Noise Ratio ADC ADC ADC Full Scale ...

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Symbol Parameter MONO Input Volume Control SS MONO Stepsize SS DAC Volume Control Stepsize DAC SS ADC Volume Control Stepsize ADC SS MIC Volume Control Stepsize MIC SV AUX Volume Setting Variation AUX SV MONO Volume Setting Variation MONO SV ...

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Typical Performance Characteristics Class D Loudspeaker Amplifier Efficiency vs Output Power THD+N < 10 Green >> LSVDD = 3.3V Gray >> LSVDD = 4.2V Blue >> LSVDD = 5V 100 ...

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DAC THD+N vs Frequency f = 8kHz, OSR = Input = 500mFFS Stereo Audio ADC Frequency Response f = 48kHz, OSR = 64 S From MIC, MIC Gain = 6dB, C Mono Voice ADC Frequency ...

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Stereo Audio HPF ADC Frequency Response f = 48kHz, OSR = 128 S From MONO/AUX, MONO>AUX Gain = 0dB, C Blue >> No HPF Light Blue >> HPF Mode = '101' Green >> HPF Mode = '110' Light Green >> ...

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ADC THD+N vs Frequency f = 48kHz, OSR = 128 S From MIC, MIC Gain = 6dB, V ADC THD+N vs Input Voltage f = 48kHz, OSR = 128 S From MIC, MIC Gain = 6dB, V Loudspeaker THD+N vs ...

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Loudspeaker THD+N vs Input Voltage From MONO/AUX Input, MONO/AUX Gain = 0dB LS Gain = 8dB, LSVDD = 3.3V 300V OUT Loudspeaker THD+N vs Output Power f = 48kHz, OSR = 128 S From MONO/AUX Input, MONO/AUX Gain ...

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Loudspeaker PSRR vs Frequency f = 48kHz, OSR = 128 S MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB LSVDD = 4.2V 200mV RIPPLE Headphone PSRR vs Frequency DAC Input, DAC Gain = 0dB, LS Gain ...

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Headphone THD+N vs Frequency MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB HPVDD = 2.8V 15mW, R OUT Stereo In Phase Headphone THD+N vs Frequency MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB HPVDD = 2.8V, ...

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Headphone THD+N vs Output Power MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB Stereo In Phase 1kHz Blue >> HPVDD = 1.8V Light Blue >> HPVDD = 2.8V Headphone PSRR vs Frequency MONO/AUX Input, ...

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Headphone Crosstalk vs Frequency MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB HPVDD = 1.8V, AVDD = 3.3V, P OUT Earpiece THD+N vs Output Power MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB AVDD = 3.3V, ...

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Auxiliary Output THD+N vs Frequency MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB AVDD = 3.3V OUT AUXOUT Mode Auxiliary Output PSRR vs FRequency MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB AVDD ...

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System Control Method Compatible Interface 12 SIGNALS mode the LM49352 pin SCL is used for the I SCL and the pin SDA is used for the I 2 ...

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Register changes take effect at the SCL rising edge during the last ACK from slave write (SDA = “0” read (SDA = “1”) ack = acknowledge (SDA pulled down by slave repeated start When ...

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TIMING PARAMETERS Symbol 1 Hold Time (repeated) START Condition 2 Clock Low Time 3 Clock High Time 4 Setup Time for a Repeated START Condition Data Hold Time (Output direction, delay generated by LM49352) 5 Data ...

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Device Register Map Address Register 7 PMC CHIP 0x00h SETUP ACTIVE PMC 0x01h CLOCKS PMC 0x02h CLK_DIV 0x03h 0x04h PLL M 0x05h PLL N PLL 0x06h N_MOD 0x07h PLL P 0x08h PLL P2 0x10h CLASSD HEAD 0x11h PHONESL HEAD ...

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Address Register 7 0x44h OPDAC 0x45h OPDECI STEREO 0x50h BASIC _SYNC _MODE 0x51h CLK_GEN1 0x52h CLK_GEN2 SYNC 0x53h _GEN DATA 0x54h TX_EXTRA_BITS _WIDTH 0x55h RX_MODE A/ULAW 0x56h TX_MODE A/ULAW STEREO 0x60h BASIC _SYNC _MODE 0x61h CLK_GEN1 0x62h CLK_GEN2 SYNC 0x63h ...

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Address Register 7 ADC L 0x89h LEVEL ADC R 0x8Ah LEVEL 0x8Bh EQ BAND 1 0x8Ch EQ BAND 2 Q 0x8Dh EQ BAND 3 Q 0x8Eh EQ BAND 4 Q 0x8Fh EQ BAND 5 SOFTCLIP 0x90h 1 SOFTCLIP 0x91h 2 ...

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Address Register 7 SOFTCLIP 0xB0h 1 SOFTCLIP 0xB1h 2 SOFTCLIP 0xB2h 3 0xB8h LVLMONL 0xB9h LVLMONR SCLP 0xBAh FXCLIP _R CLIP SCLP_R 0xBBh ALCMONL DISTORT SCLP_L 0xBCh ALCMONR DISTORT 0xE0h GPIO1 GPIO_RX 0xE1h GPIO2 0xF0h RESET 0xF1h SS 0xFEh FORCE ...

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Basic PMC Setup Register This register is used to control the LM49352's Basic Power Management Setup: Bits Field 0 CHIP_ENABLE 1 PLL_ENB 2 PLL_P2ENB 3 OSC_ENB 4 MCLK_OVR 5 PORT1_CLK_OVR 6 PORT2_CLK_OVR 7 CHIP_ACTIVE 1. If the PMC is ...

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PMC Clocks Register This register is used to control the LM49352's Basic Power Management Clock: Bits Field 1:0 PMC_CLK_SEL 16.0 PMC Clock Divide Register This register is used to control the LM49352's Power Management Circuit Clock Divider: Bits Field ...

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LM49352 Clock Network (Refer to Figure 12) The audio DAC and ADC operate at a clock frequency of 2*OSR*f frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125, 64). The ADC ...

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FIGURE 12. Internal Clock Network 39 30072713 www.national.com ...

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PLL Setup Registers The LM49352 contains a PLL for flexible operation of its dual audio ports. The PLL has a P1 and P2 output divider thereby allowing the PLL to generate two distinct clock outputs. The equations for the ...

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16.2 22.5 196 16.8 12.5 126 19.2 20 147 19.68 20.5 147 19.8 27.5 196 26 18.5 144 27 37.5 196 11.2896 10.5 195 12.288 8 125 13 6.5 102 13.5 4.5 68 14.4 6 ...

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Bits Field 6:0 PLL_M Bits Field 7:0 PLL_N Bits Field 4:0 PLL_N_MOD 5 PLL_P1[8] 6 PLL_P2[8] www.national.com TABLE 10. PLL_M (0x04h) This programs the PLL's M divider to divide from 1 to 64. PLL_M 000000 000001 000010 000011 000100 000101 ...

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Bits Field 7:0 PLL_P1[7:0] This programs the 8 LSBs of the PLL's P1 Divider. These LSBs combine with PL1_P1[8] which allows the P1 divider to divide 256. Bits Field 7:0 PLL_P2[7:0] This programs 8 LSBs of the ...

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Analog Mixer Control Registers This register is used to control the LM49352's Analog Mixer: Bits Field 0 DACR_LS 1 DACL_LS 2 RSVD 3 RSVD 4 MONO_LS 5 AUX_LS Class D Loudspeaker Amplifier The LM49352 features a filterless modulation scheme. ...

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FIGURE 14. EMI/RFI Filter for the Class D Amplifier TABLE 16. LEFT HEADPHONE_OUTPUT (0x11h) Bits Field 0 DACR_HPL 1 DACL_HPL 2 RSVD 3 RSVD 4 MONO_HPL 5 AUX_HPL TABLE 17. RIGHT HEADPHONE_OUTPUT (0x12h) Bits Field 0 DACR_HPR 1 DACL_HPR 2 ...

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Charge Pump Flying Capacitor (C5) The value and ESR of the hold capacitor (C5) directly affects the ripple on CPV Decreasing the ESR of C5 reduces both output ripple and charge pump output impedance. A lower value capacitor can be ...

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Auxiliary Output Amplifier The LM49352’s auxiliary output (AUXOUT) amplifier provides differential drive capability to loads that are connected across its outputs. This results in output signals at the AUX_OUT+ and AUX_OUT- pins that are 180 degrees out of phase with ...

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Bits Field 0 DACR_ADCR 1 DACL_ADCL 2 MIC_ADCR 3 MIC_ADCL 4 AUX_ADCR 5 MONO_ADCL Bits Field 3:0 MIC_LEVEL 4 SE_DIFF 5 MUTE www.national.com TABLE 20. ADC_INPUT (0x15h) The right DAC output is added to the ADC right input. The left ...

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TABLE 22. AUX_LEVEL (0x18h) Bits Field 5:0 AUX_LEVEL This programs the AUX input level. All gain changes are performed at zero crossings. AUX_LEVEL 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 ...

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Bits Field 5:0 MONO_LEVEL This programs the MONO input level. All gain changes are performed at zero crossings. 6 SE/DIFF If set, the MONO– input is ignored. In single-ended mode, the MONO- input pin should be left floating. 7 AUXL_MONO ...

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Headphone Detection Circuit The LM49352 features a headphone detection circuit (HDC) that automatically enables the headphone amplifier whenever the insertion of a headphone plug is detected and disables the headphone amplifier during the removal of a headphone plug. The HDC ...

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Bits Field 0 HP SENSE This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone sense input. If ...

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ADC Control Registers This register is used to control the LM49352's ADC: Bits Field 0 MONO This sets mono or stereo operation of the ADC. 1 OSR This sets the oversampling ratio of the ADC. 2 MUTE_L If set, ...

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Bits Field 1:0 ADC_MIX_LEVEL_L This sets the input level to the left ADC channel. 3.2 ADC_MIX_LEVEL_R This sets the input level to the right ADC channel. 4 STEREO_LINK If set, this links ADC_MIX_LEVEL_R with ADC_MIX_LEVEL_L. www.national.com TABLE 27. ADC_MIXER (0x23h) ...

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DAC Control Registers This register is used to control the LM49352's DAC: Bits Field 1:0 MODE This programs the over sampling ratio of the stereo DAC. 2 MUTE_L This digitally mutes the Left DAC output. 3 MUTE_R This digitally ...

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Digital Mixer Control Registers Digital Mixer The LM49352’s digital mixer allows for flexible routing of digital audio signals between both audio ports, DAC, and ADC. This mixer handles which digital data path (Port1 RX data, Port2 RX data, or ...

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This register is used to control the LM49352's digital mixer: Bits Field 1:0 PORT1_RX_L This programs the input level of the data arriving from the left receive channel of Audio Port 1. _LVL 3:2 PORT1_RX_R This programs the input level ...

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Bits Field 7:6 INTERP_R_LVL This programs the input level of the data arriving from the right DAC's interpolator output. Bits Field 1:0 L_SEL This selects which input is fed to the Left TX Channel of Audio Port 1. 3:2 R_SEL ...

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Bits Field 0 PORT1_L This adds Audio Port 1's left RX channel to the DAC's left input. 1 PORT2_L This adds Audio Port 2's left RX channel to the DAC's left input. 2 ADC_L This adds the ADC's left output ...

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Audio Port Control Registers FIGURE 18. Left Justified Data Format (24 bit example) FIGURE 19. Right Justified Data Format (24 bit example) www.national.com FIGURE 17 Serial Data Format (24 bit example) FIGURE 20. PCM Serial Data ...

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The following registers are used to control the LM49352's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers. Bits Field 0 STEREO ...

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Bits Field 2:0 SYNTH_NUM Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in master mode. 3 SYNTH_DENOM Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or ...

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Bits Field 5:3 SYNC_WIDTH In MONO mode, this programs the width (in number of bits) of the SYNC signal. SYNC_WIDTH Bits Field 2:0 RX_WIDTH This programs the expected bits per word of the serial data input SDI. 5:3 TX_WIDTH This ...

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Bits Field 0 RX_MODE This sets the RX data input justification with respect to the SYNC signal. 5:1 MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of ...

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Bits Field 0 TX_MODE This sets the TX data output justification with respect to the SYNC signal. 5:1 MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of ...

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Digital Effects Engine Digital Signal Processor (DSP) The LM49352 is designed to handle the entire audio signal conditioning and processing within the audio system, thereby freeing up the workload of any other applications processor contained within the system. The ...

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Bits Field 0 DAC_ALC_ENB This enables the DAC's Automatic Level Control. 1 DAC_PK_ENB This enables the DAC's Peak Detector. 2 DAC_EQ_ENB This enables the DAC's 5-band Parametric EQ. 3 RSVD Reserved 4 ADC_SCLP_ENB This enables the DAC's Soft Clip Feature. ...

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ALC Overview The Automatic Level Control (ALC) system can be used to regulate the audio output level to a user defined target level. The ALC feature is especially useful whenever the level of the audio input is unknown, unpredictable, or ...

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Limiter The LM49352’s ALC features a limiter function. The purpose of the limiter is to limit the maximum level of the audio signal to the specified ALC target level. When the limiter is enabled, the ALC will decrease the gain ...

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Bits Field 2:0 ADC_SAMPLE This programs the timers on the ALC with the closest sample rate of the ADC. 3 LIMITER If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate ...

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Bits Field 4:0 TARGET_LEVEL This sets the desired target output level. Signals lower than this will be amplified and signals larger than this will be attenuated. TABLE 48. ADC_ALC_3 (0x83h) Description TARGET_LEVEL 00000 00001 00010 00011 00100 00101 00110 00111 ...

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Bits Field 4:0 ATTACK_RATE This sets the rate at which the ALC will reduce gain if it detects the input signal is large. www.national.com TABLE 49. ADC_ALC_4 (0x84h) Description ATTACK_RATE 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 ...

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Bits Field 4:0 DECAY_RATE 7:5 PK_DECAY_RATE TABLE 50. ADC_ALC_5 (0x85h) Description This sets the rate at which the ALC will increase gain if it detects the input signal is too small. DECAY_RATE 00000 00001 00010 00011 00100 00101 00110 00111 ...

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Bits Field 4:0 HOLD_TIME This sets how long the ALC circuit waits before increasing the gain. Bits Field 5:0 MAX_LEVEL Bits Field 5:0 MIN_LEVEL www.national.com TABLE 51. ADC_ALC_6 (0x86h) Description HOLD_TIME 00000 00001 00010 00011 00100 00101 00110 00111 01000 ...

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TABLE 54. ADC_L_LEVEL (0x89h) Bits Field 5:0 ADC_L_LEVEL This sets the post ADC digital gain of the left channel. ADC_L_LEVEL 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 ...

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Bits Field 5:0 ADC_R_LEVEL www.national.com TABLE 55. ADC_R_LEVEL (0x8Ah) Description This sets the post ADC digital gain of the right channel. ADC_R_LEVEL Level 000000 -76.5dB 000001 -75dB 000010 -73.5dB 000011 -72dB 000100 -70.5dB 000101 -69dB 000110 -67.5dB 000111 -66dB 001000 ...

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TABLE 56. EQ_BAND_1 (0x8Bh) Bits Field 1:0 FREQ This sets the Sub-bass shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ 6:2 ...

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Bits Field 1:0 FREQ 6:2 LEVEL 7 Q www.national.com TABLE 57. EQ_BAND_2 (0x8Ch) Description This sets the Bass peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down ...

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TABLE 58. EQ_BAND_3 (0x8Dh) Bits Field 1:0 FREQ This sets the Mid peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ 6:2 ...

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Bits Field 1:0 FREQ 6:2 LEVEL 7 Q www.national.com TABLE 59. EQ_BAND_4 (0x8Eh) Description This sets the Treble peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down ...

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TABLE 60. EQ_BAND_5 (0x8Fh) Bits Field 1:0 FREQ This sets the presence shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ 6:2 ...

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Digital Audio Compressor The LM49352 features a digital audio compressor on both the DAC and ADC paths. The compressor works by reducing the level of the audio signal that is higher than the level set by the audio compressor threshold ...

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Soft Knee Function The LM49352’s audio compressor also features a soft knee function that smoothes the harsh edges found during clipping of an audio signal. For audio signals higher than the compressor threshold level, the soft knee function gradually increases ...

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Bits Field 3:0 THRESHOLD 4 SOFT_KNEE www.national.com TABLE 61. SOFTCLIP1 (0x90h) Description This sets the threshold level of the audio compressor. Audio signals above the threshold will be compressed. THRESHOLD Threshold Level (dB) 0000 0001 0010 0011 0100 0101 0110 ...

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TABLE 62. SOFTCLIP2 (0x91h) Bits Field 4:0 RATIO This sets the ratio at which the audio is compressed to when it passes beyond the threshold. In SOFT_KNEE mode this is the final level of compression. RATIO 00000 00001 00010 00011 ...

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Bits Field 3:0 LEVEL www.national.com TABLE 63. SOFTCLIP3 (0x92h) Description This sets the post compressor gain level. LEVEL 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 ...

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DAC Effects Registers Bits Field 2:0 DAC_SAMPLE 3 LIMITER 4 STEREO LINK Bits Field 3:0 NOISE_FLOOR 4 NG_ENB TABLE 64. DAC_ALC_1 (0xA0h) Description This programs the timers on the ALC with the closest DAC sample rate. DAC_SAMPLE Expected DAC ...

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Bits Field 4:0 TARGET_LEVEL This sets the desired output level. Signals lower than this will be amplified www.national.com TABLE 66. DAC_ALC_3 (0xA2h) Description and signals larger than this will be attenuated. TARGET_LEVEL Target Level (dB) 00000 00001 00010 00011 00100 ...

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TABLE 67. DAC_ALC_4 (0xA3h) Bits Field 4:0 ATTACK_RATE This sets the rate at which the ALC will reduce gain if it detects the input signal is too large. ATTACK_RATE 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 ...

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Bits Field 4:0 DECAY_RATE 7:5 PK_DECAY_RATE www.national.com TABLE 68. DAC_ALC_5 (0xA4h) Description This sets the rate at which the ALC will increase gain if it detects the input signal is too small. DECAY_RATE Time between gain steps(us) 00000 00001 00010 ...

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TABLE 69. DAC_ALC_6 (0xA5h) Bits Field 4:0 HOLD_TIME This sets how long the ALC circuit waits before increasing the gain. HOLDTIME 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 ...

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Bits Field 5:0 DAC_L_LEVEL 6 STEREO_LINK www.national.com TABLE 72. DAC_L_LEVEL (0xA8h) Description This sets the pre DAC digital gain. DAC_L_LEVEL Level 000000 -76.5dB 000001 -75dB 000010 -73.5dB 000011 -72dB 000100 -70.5dB 000101 -69dB 000110 -67.5dB 000111 -66dB 001000 -64.5dB 001001 ...

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TABLE 73. DAC_R_LEVEL (0xA9h) Bits Field 5:0 DAC_R_LEVEL This sets the pre DAC digital gain. DAC_R_LEVEL 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 ...

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Bits Field 1:0 FREQ 6:2 LEVEL www.national.com TABLE 74. EQ_BAND_1 (0xABh) Description This sets the Sub-bass shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off ...

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TABLE 75. EQ_BAND_2 (0xACh) Bits Field 1:0 FREQ This sets the Bass peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ 6:2 ...

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Bits Field 1:0 FREQ 6:2 LEVEL 7 Q www.national.com TABLE 76. EQ_BAND_3 (0xADh) Description This sets the Mid peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down ...

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TABLE 77. EQ_BAND_4 (0xAEh) Bits Field 1:0 FREQ This sets the Treble peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ 6:2 ...

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Bits Field 1:0 FREQ 6:2 LEVEL www.national.com TABLE 78. EQ_BAND_5 (0xAFh) Description This sets the presence shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off ...

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TABLE 79. SOFTCLIP1 (0xB0h) Bits Field 3:0 TRESHOLD This sets the threshold level of the audio compressor. Audio signals above the threshold will be compressed. THRESHOLD 4 SOFT_KNEE If set, the audio compressor will automatically apply higher compression ratios to ...

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Bits Field 4:0 RATIO www.national.com TABLE 80. SOFTCLIP2 (0xB1h) Description This sets the ratio at which the audio is compressed to when it passes beyond the threshold. In soft clip mode this is the final level of compression. RATIO 00000 ...

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TABLE 81. SOFTCLIP3 (0xB2h) Bits Field 4:0 LEVEL This sets the post compressor gain level. LEVEL 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 ...

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GPIO Registers Bits Field 5:0 GPIO_MODE 5:0 GPIO_MODE 6 GPIO_TX 7 GPIO_RX www.national.com TABLE 82. GPIO1 (0xE0h) Description This sets the mode of the GPIO Pin. GPIO_MODE 000000 GPIO Mode is disabled .PORT2_SDO is controlled by the Port2 serial ...

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Bits Field 0 SHORT This bit will go high whenever a short circuit condition occurs on the Class D loudspeaker amplifier outputs. Once triggered by a short circuit event this bit clear this bit. 1 ...

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Schematic Diagram www.national.com 104 ...

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Demonstration Board Layout FIGURE 28. Top Silkscreen FIGURE 29. Top Layer 105 30072721 30072782 www.national.com ...

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FIGURE 30. Inner Layer 2 FIGURE 31. Inner Layer 3 106 30072780 30072781 ...

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FIGURE 32. Bottom Layer FIGURE 33. Bottom Silkscreen 107 30072779 30072778 www.national.com ...

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Revision History Rev Date 1.0 05/03/10 1.01 06/30/10 www.national.com Description Initial released. Fixed a typo in the Timing Parameters table. 108 ...

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Physical Dimensions X = 3.281±.03mm inches (millimeters) unless otherwise noted micro SMD–36 Package Order Number LM49352RL NS Package Number RLA36MMA = 3.281±.03mm 0.65±.075mm 2 3 109 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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