LM49370RLX/NOPB National Semiconductor, LM49370RLX/NOPB Datasheet

IC AUDIO SUBSYSTEM 1.2W 49USMDXT

LM49370RLX/NOPB

Manufacturer Part Number
LM49370RLX/NOPB
Description
IC AUDIO SUBSYSTEM 1.2W 49USMDXT
Manufacturer
National Semiconductor
Series
Boomer®, PowerWise®r
Type
Class Dr
Datasheet

Specifications of LM49370RLX/NOPB

Output Type
1-Channel (Mono) with Mono and Stereo Headphones
Max Output Power X Channels @ Load
1.2W x 1 @ 8 Ohm; 52mW x 2 @ 16 Ohm
Voltage - Supply
2.5 V ~ 5.5 V
Features
3D, Depop, I²C, I²S, Microphone, Mute, PCM, Shutdown, SPI, Standby, Volume Control
Mounting Type
Surface Mount
Package / Case
49-MicroSMDxt
Operational Class
Class-D
Single Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (typ)
3/5V
Supply Current (max)
15.5@3.3VmA
Power Supply Requirement
Quint
Rail/rail I/o Type
No
Power Supply Rejection Ratio
86dB
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
1.8/2.5V
Dual Supply Voltage (max)
4.5/5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
49
For Use With
LM49370RLEVAL - BOARD EVALUATION LM49370RL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LM49370RLX

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM49370RLX/NOPB
Manufacturer:
NS
Quantity:
3 186
© 2008 National Semiconductor Corporation
LM49370
Audio Sub-System with an Ultra Low EMI, Spread
Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode
Stereo Headphone Amplifier, and a Dedicated PCM
Interface for Bluetooth Transceivers
1.0 General Description
The LM49370 is an integrated audio subsystem that supports
both analog and digital audio functions. The LM49370 in-
cludes a high quality stereo DAC, a mono ADC, a stereo
headphone amplifier, which supports output cap-less (OCL)
or AC-coupled (SE) modes of operation, a mono earpiece
amplifier, and an ultra-low EMI spread spectrum Class D
loudspeaker amplifier. It is designed for demanding applica-
tions in mobile phones and other portable devices.
The LM49370 features a bi-directional I
directional PCM interface for full range audio on either inter-
face. The LM49370 utilizes an I
for control. The stereo DAC path features an SNR of 85 dB
with an 18-bit 48 kHz input. In SE mode the headphone am-
plifier delivers at least 33 mW
stereo load with less than 1% distortion (THD+N) when
A_V
115mW
tortion (THD+N) when A_V
amplifier delivers up to 490mW into an 8Ω load with less than
1% distortion when LS_V
LS_V
The LM49370 employs advanced techniques to reduce pow-
er consumption, to reduce controller overhead, to speed de-
velopment time, and to eliminate click and pop. Boomer audio
power amplifiers were designed specifically to provide high
quality output power with a minimal amount of external com-
ponents. It is therefore ideally suited for mobile phone and
other low voltage applications where minimal power con-
sumption, PCB area and cost are primary requirements.
2.0 Applications
3.0 Key Specifications
Boomer® is a registered trademark of National Semiconductor Corporation.
Smart phones
Mobile Phones and Multimedia Terminals
PDAs, Internet Appliances and Portable Gaming
Portable DVD/CD/AAC/MP3 Players
Digital Cameras/Camcorders
P
P
P
P
P
Shutdown Current
PSRR
DD
HP (AC-COUP)
HP (OCL)
LS
LS
LS
DD
= 3.3V. The mono earpiece amplifier delivers at least
( LS_V
(LS_V
(LS_V
RMS
= 5.0V.
LS
to a 32Ω bridged-tied load with less than 1% dis-
(217 Hz, LS_V
(A_V
DD
DD
DD
(A_V
= 4.2V, 8Ω, 1% THD)
= 3.3V, 8Ω, 1% THD)
= 5V, 8Ω, 1% THD)
DD
= 3.3V, 32Ω, 1% THD)
DD
= 3.3V, 32Ω, 1% THD)
DD
DD
DD
= 3.3V and up to 1.2W when
= 3.3V)
2
C or SPI compatible interface
= 3.3V. The mono speaker
RMS
to a 32Ω single-ended
2
S interface and a bi-
201917
900 mW
490 mW
33 mW
31 mW
0.8 µA
1.2 W
70 dB
4.0 Features
SNR
SNR
SNR
SNR
Spread Spectrum Class D architecture reduces EMI
Mono Class D 8Ω amplifier, 490 mW at 3.3V
OCL or AC-coupled headphone operation
33mW stereo headphone amplifier at 3.3V
115 mW earpiece amplifier at 3.3V
18-bit stereo DAC
16-bit mono ADC
8 kHz to 192 kHz stereo audio playback
8 kHz to 48 kHz mono recording
Bidirectional I
Bidirectional PCM compatible audio interface for
Bluetooth transceivers
I
Sigma-Delta PLL for operation from any clock at any
sample rate
Digital 3D Stereo Enhancement
FIR filter programmability for simple tone control
Low power clock network operation if a 12 MHz or 13 MHz
system clock is available
Read/write I
Automatic headphone & microphone detection
Support for internal and external microphones
Automatic gain control for microphone input
Differential audio I/O for external cellphone module
Mono differential auxiliary output
Stereo auxiliary inputs
Differential microphone input for internal microphone
Flexible audio routing from input to output
32 Step volume control for mixers in 1.5 dB steps
16 Step volume control for microphone in 2 dB steps
Programmable sidetone attenuation in 3 dB steps
Two configurable GPIO ports
Multi-function IRQ output
Micro-power shutdown mode
Available in the 4 x 4 mm 49 bump micro SMDxt package
2
S-PCM Bridge with sample rate conversion
LS
DAC
ADC
HP
(AUX IN to Loudspeaker)
(Aux In to Headphones)
(Stereo DAC to AUXOUT)
(Mono ADC from Cell Phone In)
2
C or SPI compatible control interface
2
S compatible audio interface
February 11, 2008
www.national.com
90 dB (typ)
85 dB (typ)
90 dB (typ)
98 dB (typ)

Related parts for LM49370RLX/NOPB

LM49370RLX/NOPB Summary of contents

Page 1

... THD ■ Shutdown Current ■ PSRR (217 Hz, LS_V = 3.3V Boomer® registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation ■ SNR (AUX IN to Loudspeaker) LS ■ SNR (Stereo DAC to AUXOUT) DAC ■ SNR (Mono ADC from Cell Phone In) ADC ■ ...

Page 2

LM49370 Overview www.national.com FIGURE 1. Conceptual Schematic 2 20191724 ...

Page 3

Typical Application FIGURE 2. Example Application in Multimedia Mobile Phone 3 20191723 www.national.com ...

Page 4

General Description ......................................................................................................................... 1 2.0 Applications .................................................................................................................................... 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Features ........................................................................................................................................ 1 5.0 LM49370 Overview .......................................................................................................................... 2 6.0 Typical Application ........................................................................................................................... 3 7.0 Connection Diagrams ....................................................................................................................... 5 7.1 PIN TYPE DEFINITIONS ................................................................................................................ 7 8.0 ...

Page 5

Connection Diagrams 49 Bump micro SMDxt Top View (Bump Side Down) Order Number LM49370RL See NS Package Number RLA49UUA 49 Bump micro SMDxt Marking XY — Date Code TT — Die Traceability G — Boomer I3 — LM49370RL 201917p3 ...

Page 6

Pin Descriptions Pin Pin Name Type Direction A1 EP_NEG Analog Output A2 A_V Supply Input DD A3 INT_MIC_POS Analog Input A4 PCM_SDO Digital Output A5 PCM_CLK Digital Inout A6 PCM_SYNC Digital Inout A7 PCM_SDI Digital Input B1 A_V Supply Input ...

Page 7

Pin Pin Name Type Direction G6 D_V Supply Input SS G7 MCLK Digital Input 7.1 PIN TYPE DEFINITIONS Analog Input— A pin that is used by the analog and is never driven by the device. Supplies are part of this ...

Page 8

... Absolute Maximum Ratings Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage (A_V & LS_V ) DD DD Digital Supply Voltage  (BB_V & D_V & PLL_V ) Storage Temperature Power Dissipation (Note 3) ...

Page 9

Symbol Parameter LOUDSPEAKER AMPLIFIER P Max Loudspeaker Power LS LS Loudspeaker Harmonic Distortion THD+N LS Efficiency EFF Power Supply Rejection Ration PSRR LS (Loudspeaker) SNR Signal to Noise Ratio LS e Output Noise N V Loudspeaker Offset Voltage OS HEADPHONE ...

Page 10

Symbol Parameter P Earpiece Power EP Power Supply Rejection Ratio PSRR EP (Earpiece) SNR Signal to Noise Ratio EP EP Earpiece Harmonic Distortion THD+N e Output Noise N V Offset Voltage OS AUXOUT AMPLIFIER THD+N Total Harmonic Distortion + Noise ...

Page 11

Symbol Parameter f PCM CLK Frequency PCMCLK DC I2S_CLK Duty Cycle I2S_CLK DC I2S_WS Duty Cycle I2S_WS I2C T I2C Data Setup Time I2CSET T I2C Data Hold Time I2CHOLD SPI T Enable Setup Time SPISETENB T Enable Hold Time ...

Page 12

Symbol Parameter Headphone Audio Path Gain Earpiece Audio Path Gain AUXOUT Audio Path Gain CPOUT Audio Path Gain www.national.com Conditions Minimum Gain from AUX input, BOOST OFF Maximum Gain from AUX input, BOOST OFF Minimum Gain from CPI input Maximum ...

Page 13

Symbol Parameter Total DC Power Dissipation Digital Playback Mode Power Dissipation Analog Playback Mode Power Dissipation VOICE CODEC Mode Power Dissipation VOICE Module Mode Power Dissipation Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may ...

Page 14

System Control Method Compatible Interface 11 SIGNALS mode the LM49370 pin SCL is used for the I signals need a pull-up resistor according ...

Page 15

Register changes take an effect at the SCL rising edge during the last ACK from slave write (SDA = “0” read (SDA = “1”) ack = acknowledge (SDA pulled down by slave repeated start ...

Page 16

When a READ function accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 11 TIMING PARAMETERS Symbol 1 Hold Time (repeated) START Condition 2 Clock Low Time ...

Page 17

Method 2. SPI/Microwire Control/3–wire Control The LM49370 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this control method connect SPI_MODE to BB_V If the application requires read access ...

Page 18

Status & Control Registers (The default value of all I2C registers is 0x00h) Addre Register 7 ss 0x00h BASIC DAC_ MODE 0x01h CLOCKS 0x02h PLL_M FORCERQ 0x03h PLL_N 0x04h PLL_P VCOFATS 0x05h PLL_MOD PLLTEST 0x06h ADC_1 HPF_MODE 0x07h ADC_2 ...

Page 19

BASIC CONFIGURATION REGISTER This register is used to control the basic function of the chip. Bits Field 1:0 CHIP_MODE The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode is ...

Page 20

CLOCKS CONFIGURATION REGISTER This register is used to control the clocks throughout the chip. Bits Field 1:0 DAC_CLK This selects the clock to be used by the audio DAC system. 7:2 R_DIV This programs the R divider. www.national.com TABLE ...

Page 21

LM49370 CLOCK NETWORK The audio ADC operates at 125* 128*fs requires a 1.000 MHz (or 1.024MHz) clock to sample at 8 kHz (at point C as marked on the following diagram). If the stereo DAC ...

Page 22

COMMON CLOCK SETTINGS FOR THE DAC & ADC When DAC_MODE = '00' (bits 7:6 of (0x00h)), the DAC has an over sampling ratio of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution ...

Page 23

PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input section of the PLL. (Note 12) Bits Field 0 RSVD 6:0 PLL_M 7 FORCERQ If set, the R and Q divider are enabled and the DAC ...

Page 24

PLL N DIVIDER CONFIGURATION REGISTER This register is used to control the feedback divider of the PLL. (Note 13) Bits Field 7:0 PLL_N This programs the PLL feedback divider as follows: The N divider should be set such that ...

Page 25

PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the output divider of the PLL. (Note 14) Bits Field 3:0 PLL_P This programs the PLL output divider as follows: 6:4 Q_DIV This programs the Q Divider 7 ...

Page 26

PLL N MODULUS CONFIGURATION REGISTER This register is used to control the modulation applied to the feedback divider of the PLL. (Note 15) Bits Field 4:0 PLL_N_MOD This programs the PLL N divider's fractional component: 6:5 PLL_CLK_SEL This selects ...

Page 27

FURTHER NOTES ON PLL PROGRAMMING The sigma-delta PLL Is designed to drive audio circuits requiring accurate clock frequencies 30MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact ...

Page 28

TABLE 11. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 01 F (MHz) F (kHz 12 26.5 14.4 48 37.5 16.2 48 37.5 16.8 48 12.53 19.2 ...

Page 29

These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done by increasing the P divider value or using the R/Q dividers. An example of obtaining 12.000 MHz from 1.536 MHz ...

Page 30

ADC_1 CONFIGURATION REGISTER This register is used to control the LM49370's audio ADC. Bits Field 0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal. 1 CPI_SELECT If set the cell phone input is ...

Page 31

ADC_2 CONFIGURATION REGISTER This register is used to control the LM49370's audio ADC. Bit Field s 0 ADC_MODE This sets the oversampling ratio of the ADC 1 ADC_MUTE If set, the analog inputs to the ADC are muted. 4:2 ...

Page 32

AGC_1 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. (Note 17) Bit Field s 0 AGC_ENABLE If set, the AGC controls the analog microphone preamplifier gain into the system. This feature is useful for ...

Page 33

AGC_2 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. Bits Field 3:0 AGC_MAX_GAIN This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier. AGC_MAX_GAIN 0100 6:4 AGC_DECAY This programs ...

Page 34

AGC_3 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. (Note 19) Bits Field 4:0 AGC_HOLDTIME This programs the amount of delay before the AGC algorithm begins to adjust the gain of the microphone preamplifier. ...

Page 35

AGC OVERVIEW The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level of the source is unknown. A target level for the output is set so ...

Page 36

MIC_1 CONFIGURATION REGISTER This register is used to control the microphone configuration. Bits Field 3:0 PREAMP_GAIN This programs the gain applied to the microphone preamplifier if the AGC is not in use. 4 MIC_MUTE If set, the microphone preamplifier ...

Page 37

MIC_2 CONFIGURATION REGISTER This register is used to control the microphone configuration. Bits Field 0 OCL_ This selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the VCM_ available supply and the ...

Page 38

SIDETONE ATTENUATION REGISTER This register is used to control the analog sidetone attenuation. (Note 21) Bits Field 3:0 SIDETONE_ This programs the attenuation applied to the microphone preamp output to produce a sidetone signal. ATTEN Note 21: An active ...

Page 39

AUX_LEFT CONFIGURATION REGISTER This register is used to control the left aux analog input. Bits Field 4:0 AUX_ This programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (Note 22) LEFT_ AUX_LEFT_LEVEL LEVEL 00100 to ...

Page 40

DAC CONFIGURATION REGISTER This register is used to control the DAC levels to the mixer. Bits Field 4:0 DAC_LEVEL This programs the gain/attenuation applied to the DAC input to the mixer. (Note 24) 00100 to 11100 5 DAC_BOOST If ...

Page 41

CP_OUTPUT CONFIGURATION REGISTER This register is used to control the differential cell phone output. (Note 25) Bit Field s 0 MIC_SELECT If set, the microphone channel of the mixer is added to the CP_OUT output signal. 1 RIGHT_SELECT If ...

Page 42

HP_OUTPUT CONFIGURATION REGISTER This register is used to control the stereo headphone output. (Note 28) Bits Field 0 SIDETONE_SELECT If set, the sidetone channel of the mixer is added to both of the headphone output signals. 1 CPI_SELECT If ...

Page 43

DETECT CONFIGURATION REGISTER This register is used to control the headset detection system. Bits Field 0 DET_INT If set, an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ ...

Page 44

HEADSET DETECT OVERVIEW The LM49370 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM49370 updates read-only ...

Page 45

FIGURE 8. Headset Configurations Supported by the LM49370 The wiring of the headset jack to the LM49370 will depend on the intended mode of the headphone amplifier: 45 20191713 www.national.com ...

Page 46

FIGURE 9. Connection of Headset Jack to LM49370 Depends on the Mode of the Headphone Amplifier. www.national.com 46 20191714 ...

Page 47

STATUS REGISTER This register is used to report the status of the device. Bits Field 0 HEADSET This field is high when headset presence is detected (only valid if the detection system is enabled). (Note 30) 1 STEREO_ This ...

Page 48

CONFIGURATION REGISTER This register is used to control the configuration of the 3D circuit. Bits Field 0 3D_ENB Setting this bit enables the 3D effect. When cleared to zero, the 3D effect is disabled and the 3D module ...

Page 49

I2S PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. Bits Field 0 I2S_OUT_ENB If set, the I gated. 1 I2S_IN_ENB If set, the I 2 I2S_MODE This programs the format of the I ...

Page 50

I2S PORT CLOCK CONFIGURATION REGISTER This register is used to control the audio data interfaces. Bit Field s 0 I2S_CLOCK_MS If set, then I driven by the device slave. 1 I2S_CLOCK_SOURCE This selects the source of the clock to ...

Page 51

DIGITAL AUDIO DATA FORMATS master mode can only be used when the DAC is enabled unless the FORCE_RQ bit is set. PCM Master mode can only be used when the ADC is enabled, unless the FORCE_RQ ...

Page 52

PCM PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. Bits Field 0 PCM_OUT_ENB If set, the PCM output bus is enabled. If this bit is cleared, thr PCM output will be tristate and ...

Page 53

PCM PORT CLOCK CONFIGURATION REGISTER This register is used to control the configuration of audio data interfaces. Bits Field 3:0 PCM_CLOCK_ This programs a clock divider that divides the clock defined by PCM_CLOCK_SOURCE reg GEN_MODE (0x1Ch). The divided clock ...

Page 54

SRC CONFIGURATION REGISTER This register is used to control the configuration of the Digital Routing interfaces. (Note 33) Bits Field 0 PCM_TX_SEL 2:1 I2S_TX_SEL 4:3 DAC_INPUT_SEL 5 MONO_SUM_SEL 7:6 MONO_SUM_MODE Note 33: Please refer to the Application Note AN-1591 ...

Page 55

FIGURE 14 PCM Bridge 55 201917r2 www.national.com ...

Page 56

GPIO CONFIGURATION REGISTER This register is used to control the GPIOs and to control the digital signal routing when using the ADC and DAC to perform sample rate conversion. Bits Field 2:0 GPIO_1_SEL This configures the GPIO_1 pin. 5:3 ...

Page 57

Sample Rate 48kHz 48kHz For DAC_MODE = '00 and '01', the defaults should be sufficient; but for DAC_MODE = '10' and '11', care should be taken to ensure the widest bandwidth is available without requiring such a large attenuation at ...

Page 58

Typical Performance Characteristics (For all performance curves AV refers to the voltage applied to the A_V DD to the D_V and PLL_V pins Stereo DAC Frequency Response f = 8kHz S Stereo DAC Frequency Response f ...

Page 59

Stereo DAC Frequency Response f = 32kHz S 20191711 Stereo DAC Frequency Response f = 48kHz S 20191718 THD+N vs Stereo DAC Input Voltage (0dB DAC, AUXOUT) 20191720 Stereo DAC Frequency Response Zoom f = 32kHz S Stereo DAC Frequency ...

Page 60

MONO ADC Frequency Response f = 8kHz, 6dB MIC S MONO ADC Frequency Response f = 8kHz, 36dB MIC S MONO ADC Frequency Response f = 16kHz, 6dB MIC S www.national.com MONO ADC Frequency Response Zoom f S 20191722 MONO ...

Page 61

MONO ADC Frequency Response f = 16kHz, 36dB MIC S 20191747 MONO ADC Frequency Response f = 24kHz, 6dB MIC S 20191749 MONO ADC Frequency Response f = 24kHz, 36dB MIC S 20191751 MONO ADC Frequency Response Zoom f = ...

Page 62

MONO ADC Frequency Response f = 32kHz, 6dB MIC S MONO ADC Frequency Response f = 32kHz, 36dB MIC S MONO ADC HPF Frequency Response f = 8kHz, 36dB MIC S (from left to right: HPF_MODE '00', '10', '01') www.national.com ...

Page 63

MONO ADC HPF Frequency Response f = 24kHz, 36dB MIC S (from left to right: HPF_MODE '00', '10', '01') MONO ADC THD+N vs MIC Input Voltage (f = 8kHz, 6dB MIC) S MONO ADC PSRR vs Frequency AV = 3.3V, ...

Page 64

MONO ADC PSRR vs Frequency AV = 3.3V, 36dB MIC DD AUXOUT PSRR vs Frequency AV = 3.3V, 0dB AUX DD (AUX inputs terminated) AUXOUT PSRR vs Frequency AV = 3.3V, 0dB CPI DD (CPI inputs terminated) www.national.com MONO ADC ...

Page 65

AUXOUT PSRR vs Frequency AV = 3.3V, 0dB DAC DD (DAC inputs selected) 20191771 CPOUT PSRR vs Frequency AV = 3.3V, 0dB AUX DD (AUX inputs terminated) 20191773 CPOUT PSRR vs Frequency AV = 3.3V, 0dB DAC DD (DAC inputs ...

Page 66

Earpiece PSRR vs Frequency AV = 3.3V, 0dB AUX DD (AUX inputs terminated) Earpiece PSRR vs Frequency AV = 3.3V, 0dB CPI DD (CPI input terminated) Earpiece PSRR vs Frequency AV = 3.3V, 0dB DAC DD (DAC input selected) www.national.com ...

Page 67

Headphone PSRR vs Frequency AV = 3.3V, 0dB AUX, OCL 1.2V DD (AUX inputs terminated) 20191783 Headphone PSRR vs Frequency AV = 3.3V, 0dB CPI, OCL 1.2V DD (CPI input terminated) 20191785 Headphone PSRR vs Frequency AV = 3.3V, 0dB ...

Page 68

Headphone PSRR vs Frequency AV = 3.3V, 0dB AUX, OCL 1.5V DD (AUX inputs terminated) Headphone PSRR vs Frequency AV = 3.3V, 0dB CPI, OCL 1.5V DD (CPI input terminated) Headphone PSRR vs Frequency AV = 3.3V, 0dB DAC, OCL ...

Page 69

Headphone PSRR vs Frequency AV = 3.3V, 0dB AUX (AUX inputs terminated) 20191795 Headphone PSRR vs Frequency AV = 3.3V, 0dB CPI (CPI input terminated) 20191797 Headphone PSRR vs Frequency AV = 3.3V, 0dB DAC, SE ...

Page 70

Loudspeaker PSRR vs Frequency AV = 3.3V, 0dB AUX DD (AUX inputs terminated) Loudspeaker PSRR vs Frequency AV = 3.3V, 0dB CPI DD (CPI input terminated) Loudspeaker PSRR vs Frequency AV = 3.3V, 0dB DAC DD (DAC input selected) www.national.com ...

Page 71

INT/EXT MICBIAS PSRR vs Frequency AV = 3.3V, MICBIAS = 2.0V DD 201917a1 INT/EXT MICBIAS PSRR vs Frequency AV = 3.3V, MICBIAS = 2.5V DD 201917a3 INT/EXT MICBIAS PSRR vs Frequency AV = 3.3V, MICBIAS = 2.8V DD 201917a5 INT/EXT ...

Page 72

INT/EXT MICBIAS PSRR vs Frequency AV = 5V, MICBIAS = 3.3V DD AUXOUT THD+N vs Frequency AV = 5V, 0dB OUT CPOUT THD+N vs Frequency AV = 5V, 0dB OUT www.national.com 201917a7 = 1V , 5kΩ ...

Page 73

Earpiece THD+N vs Frequency AV = 5V, 0dB 50mW, 32Ω DD OUT 201917b3 Headphone THD+N vs Frequency AV = 5V, OCL 1.5V, 0dB 10mW, 32Ω OUT 201917b5 Headphone THD+N vs Frequency AV = 5V, OCL ...

Page 74

Headphone THD+N vs Frequency AV = 5V, SE, 0dB 10mW, 32Ω OUT Loudspeaker THD+N vs Frequency OUT 15μH+8Ω+15μH Earpiece THD+N vs Output Power AV = 5V, 0dB AUX 1kHz, ...

Page 75

Earpiece THD+N vs Output Power AV = 5V, 0dB AUX 1kHz, 32Ω OUT 201917c3 Earpiece THD+N vs Output Power AV = 5V, 0dB CPI 1kHz, 16Ω OUT 201917c5 Earpiece THD+N vs Output Power AV ...

Page 76

Headphone THD+N vs Output Power AV = 5V, OCL 1.2V, 0dB DAC 1kHz, 16Ω OUT Headphone THD+N vs Output Power AV = 5V, OCL 1.2V, 0dB DAC 1kHz, 32Ω OUT Headphone THD+N vs Output ...

Page 77

Headphone THD+N vs Output Power AV = 5V, OCL 1.2V, 12dB DAC 1kHz, 32Ω OUT 201917d5 Headphone THD+N vs Output Power AV = 5V, OCL 1.5V, 0dB DAC 1kHz, 16Ω OUT 201917d7 Headphone THD+N ...

Page 78

Headphone THD+N vs Output Power AV = 5V, OCL 1.5V, 12dB DAC 1kHz, 16Ω OUT Headphone THD+N vs Output Power AV = 5V, OCL 1.5V, 12dB DAC 1kHz, 32Ω OUT Headphone THD+N vs Output ...

Page 79

Headphone THD+N vs Output Power AV = 5V, SE, 0dB DAC 1kHz, 32Ω OUT 201917e7 Headphone THD+N vs Output Power AV = 5V, SE, 12dB DAC 1kHz, 16Ω OUT 201917e9 Headphone THD+N vs Output ...

Page 80

Headphone THD+N vs Output Power AV = 3.3V, OCL 1.2V, 12dB AUX 1kHz, 16Ω OUT Headphone THD+N vs Output Power AV = 5V, OCL 1.2V, 12dB AUX 1kHz, 16Ω OUT Headphone THD+N vs Output ...

Page 81

Headphone THD+N vs Output Power AV = 5V, OCL 1.2V, 12dB AUX 1kHz, 32Ω OUT 201917f9 Headphone THD+N vs Output Power AV = 5V, OCL 1.2V, 0dB CPI 1kHz, 16Ω OUT 201917g1 Headphone THD+N ...

Page 82

Headphone THD+N vs Output Power AV = 3.3V, OCL 1.5V, 12dB AUX 1kHz, 16Ω OUT Headphone THD+N vs Output Power AV = 5V, OCL 1.5V, 12dB AUX 1kHz, 16Ω OUT Headphone THD+N vs Output ...

Page 83

Headphone THD+N vs Output Power AV = 5V, OCL 1.5V, 12dB AUX 1kHz, 32Ω OUT 201917h1 Headphone THD+N vs Output Power AV = 5V, OCL 1.5V, 0dB CPI 1kHz, 16Ω OUT 201917h3 Headphone THD+N ...

Page 84

Headphone THD+N vs Output Power AV = 5V, SE, 0dB AUX 1kHz, 16Ω OUT Headphone THD+N vs Output Power AV = 5V, SE, 0dB AUX 1kHz, 32Ω OUT Headphone THD+N vs Output Power AV ...

Page 85

Headphone THD+N vs Output Power AV = 5V, SE, 0dB CPI 1kHz, 32Ω OUT 201917i3 Loudspeaker THD+N vs Output Power AV = 4.2V, 0dB AUX 1kHz, 15μH+8Ω+15μH OUT 20191739 Loudspeaker THD+N vs Output Power ...

Page 86

Loudspeaker THD+N vs Output Power AV = 5V, 0dB CPI 1kHz, 15μH+8Ω+15μH OUT Loudspeaker THD+N vs Output Power AV = 4.2V, 0dB DAC 1kHz, 15μH+8Ω+15μH OUT AUXOUT THD+N vs Output Voltage AV = 3.3V, ...

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AUXOUT THD+N vs Output Voltage AV = 3.3V, 0dB CPI 1kHz, 5kΩ OUT 201917i6 AUXOUT THD+N vs Output Voltage AV = 3.3V, 0dB DAC 1kHz, 5kΩ OUT 201917i8 AUXOUT THD+N vs Output Voltage AV ...

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CPOUT THD+N vs Output Voltage AV = 3.3V, 0dB AUX 1kHz, 5kΩ OUT CPOUT THD+N vs Output Voltage AV = 3.3V, 0dB DAC 1kHz, 5kΩ OUT CPOUT THD+N vs Output Voltage AV = 3.3V, ...

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CPOUT THD+N vs Output Voltage AV = 3.3V, 12dB DAC 1kHz, 5kΩ OUT 201917j8 CPOUT THD+N vs Output Voltage AV = 3.3V, 36dB MIC 1kHz, 5kΩ OUT 201917k0 Headphone Crosstalk vs Frequency OCL 1.2V, ...

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Headphone Crosstalk vs Frequency SE, 0dB AUX, 32Ω www.national.com 201917k4 90 ...

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LM49370 Demonstration Board Schematic Diagram 91 www.national.com ...

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Demoboard PCB Layout www.national.com Top Silkscreen 92 201917z9 ...

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Top Layer 93 201917z8 www.national.com ...

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Mid Layer 1 94 201917z6 ...

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Mid Layer 2 95 201917z7 www.national.com ...

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Bottom Layer 96 201917z4 ...

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Bottom Silkscreen 97 201917z5 www.national.com ...

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Revision History Rev 1.0 1.01 1.02 www.national.com Date 02/14/07 Initial release. 01/08/08 Fixed a typo on X3 value (Physical Dimension section) in the last page. 02/11/08 Text edits. 98 Description ...

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Physical Dimensions Dimensions 3.924±0.03mm 3.924±0.03mm 0.650±0.075mm inches (millimeters) unless otherwise noted 49 Bump micro SMDxt Package Order Number LM49370RL NS Package Number RLA49UUA 99 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...

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