LC89960 Sanyo Semiconductor Corporation, LC89960 Datasheet

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LC89960

Manufacturer Part Number
LC89960
Description
NTSC 1H delay line
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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Ordering number : EN4544A
Overview
The LC89960 and LC89960M are delay lines and produce
a 1H delayed signal for the NTSC format, with an external
low-pass filter.
Functions
• 905-stage shift register
• Auto-bias circuit
• Sync tip clamp circuit
• Sample-and-hold circuit
• PLL 4 frequency multiplier circuit
• VCO (4 fsc) output circuit
Features
• Single 5 V power supply
• The provision of a built-in 4
• Built-in peripheral circuits allow operation with
• Positive phase signal input, reverse phase signal output
Specifications
Absolute Maximum Ratings at Ta = 25°C
Maximum supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
circuit allows the LC89960, 89960M to operate as a
high bandwidth delay line from a 3.58 MHz clock input.
minimal external circuits.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Parameter
frequency multiplier
V
Symbol
Pd max
DD
Topr
Tstg
max
LC89960
LC89960M
Package Dimensions
unit: mm
3003A-DIP14
unit: mm
3034A-MFP14
Conditions
LC89960, 89960M
53098HA (OT) /42895TH (OT) No. 4544-1/4
NTSC 1H Delay Line
[LC89960M]
[LC89960]
–0.3 to +6.0
–55 to +125
–10 to +60
Ratings
SANYO: MFP14
450
250
SANYO: DIP14
MOS IC
Unit
mW
mW
°C
°C
V

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LC89960 Summary of contents

Page 1

... Ordering number : EN4544A Overview The LC89960 and LC89960M are delay lines and produce a 1H delayed signal for the NTSC format, with an external low-pass filter. Functions • 905-stage shift register • Auto-bias circuit • Sync tip clamp circuit • Sample-and-hold circuit • PLL 4 frequency multiplier circuit • ...

Page 2

... Supply voltage V DD Clock input amplitude V CLK Clock frequency F CLK Signal input amplitude V IN Note: * Since sync tip clamping is normally performed, the input signal must be connected in a low impedance state. Pin Assignment Block Diagram LC89960, 89960M Conditions Sine wave * Pin Functions Pin No ...

Page 3

... N O Output impedance Z O Delay time T D Note: 1. Input signal/output signal 2. Input signal/output signal LC89960, 89960M = 5.0 V, CLK = 3.579545 MHz; 500 mVp-p DD Conditions No signal input With a 200 kHz 0.5 Vp-p input 3.58 MHz, 0.2 Vp-p/200 kHz, 0.2 Vp signal input, the 4 fsc component No signal input, 0 ...

Page 4

... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of May, 1998. Specifications and information herein are subject to change without notice. LC89960, 89960M 1H delay output (positive phase) PS No. 4544-4/4 ...

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