TP3420AJ National Semiconductor, TP3420AJ Datasheet

no-image

TP3420AJ

Manufacturer Part Number
TP3420AJ
Description
ISDN S/T Interface Device
Manufacturer
National Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TP3420AJ
Manufacturer:
NS
Quantity:
6 270
Company:
Part Number:
TP3420AJ
Quantity:
20
© 1999 National Semiconductor Corporation
TP3420A
ISDN S/T Interface Device
General Description
The TP3420A is an enhanced version of the TP3420, with a
number of upgraded features for compliance with the new
release of ANSI T1.605-1991 and CCITT I-430. At initial
power-up the device is fully backwards compatible with the
TP3420 device, and modifications to the firmware are only
required to take advantage of the new features.
The TP3420A S Interface Device (SID
monolithic transceiver for data transmission on twisted pair
subscriber loops. It is built on National’s advanced 1.0 mi-
cron double-metal CMOS process, and requires only a
single +5V supply. All functions specified in CCITT recom-
mendation I.430 (1991) and ANSI T1.605 (1991) for ISDN
basic access at the “S” and “T” interfaces are provided, and
the device can be configured to operate either in a TE (Ter-
minal Equipment), in an NT-1 or NT-2 (Network Termination)
or as a PABX line-card or trunk-card device.
As specified in I.430, full-duplex transmission at 192 kb/s is
provided on separate transmit and receive twisted wire pairs
using inverted Alternate Mark Inversion (AMI) line coding. 2
“B” channels, each of 64 kb/s, and 1 “D” channel at 16 kb/s
are available for users’ data. In addition, the TP3420A pro-
vides the 800 b/s “S1”, “S2” & “Q” multiframe channels for
Layer 1 maintenance.
All I.430 wiring configurations are supported by the TP3420A
SID, including the “passive bus” for up to 8 TE’s distributed
within 200 meters of low capacitance cable, and
point-to-point and point-to-star connections up to at least
1500 meters (24AWG). Adaptive receive signal processing
ensures low bit error rates on any of the standard types of
cable pairs commonly found in premise wiring installations
when tested with the noise sources specified in I.430.
TRI-STATE
COMBO
, MICROWIRE
®
is a registered trademark of National Semiconductor Corporation.
and SID
are trademarks of National Semiconductor Corporation.
DS009143
) is a complete
Features
n 2 B + D 4-wire 192 kb/s transceiver
n Selectable TE or NT mode
n Exceeds I.430 range: 1.5 km point-to-point
n Adaptive receiver for high noise immunity
n Adaptive and fixed timing options for NT-1
n Clock resynchronizer and elastic buffers for NT-2/LT
n Slave-slave mode for NT-2 trunks
n Extensive hardware support for SC1, SC2 and Q
n Bipolar violation detection and FECV messaging
n Selectable system interface formats
n MICROWIRE
n TP3054/7 Codec/Filter COMBO
n Single +5V supply
n 20-pin package DIP, PLCC
Applications
n Same Device for NT, TE and PBX Line Card
n Point-to-Point Range Extended to 1.5 km
n Point-to-Multipoint for all I.430 Configurations
n Easy Interface to:
n Line Monitor Mode for Test Equipment
channel messaging
interface
LAPD Processor MC68302, HPC16400
Terminal Adapter MC68302, HPC16400
Codec/Filter COMBO TP3054/7 and TP3076
“U” Interface Device TP3410
Line Card Backplanes — No External PLL Needed
and SCP compatible serial control
PRELIMINARY
compatibility
www.national.com
July 1994

Related parts for TP3420AJ

TP3420AJ Summary of contents

Page 1

... Adaptive receive signal processing ensures low bit error rates on any of the standard types of cable pairs commonly found in premise wiring installations when tested with the noise sources specified in I.430. TRI-STATE ® registered trademark of National Semiconductor Corporation. COMBO ™ , MICROWIRE ™ and SID ™ ...

Page 2

... Block Diagram Connection Diagrams TP3420A SID Order Number TP3420AV See NS Package Number V20A TP3420A SID Top View Order Number TP3420AJ or TP3420AN See NS Package Number J20A or N20A www.national.com Pin Descriptions Name GND Negative power supply pin, normally 0V (ground). All analog and digital signals are referenced to this pin ...

Page 3

Pin Descriptions (Continued) Name Description modes and TES mode, this pin is a the Transmit Frame Sync pulse TTL/CMOS input, requiring a positive edge to indicate the start of the active channel time for transmit “B” and ...

Page 4

Pin Descriptions (Continued) TABLE 1. Alternate Pin Function Assignment Device P2 - Pin 8 Mode Function x Function 2 TEM DENx 0 LSD (Note 3) (Note 3) SCLK 1 DENr SCLK DENx TES DENx 0 LSD SCLK 1 DENr (Note ...

Page 5

Functional Description (Continued) + − boundary, by using a 0 bit followed dicate the start of a frame, and forcing the first binary zero following the balance bit the same polarity as the bal- ...

Page 6

Functional Description www.national.com (Continued) 6 ...

Page 7

Functional Description (Continued) DIGITAL SYSTEM INTERFACE The Digital System Interface (DSI) on the TP3420A com- bines “B” and “D” channel data onto common pins to provide maximum flexibility with minimum pin count. Several multi- plexed formats of the B and ...

Page 8

Functional Description Note: In TES mode, DENx outputs SCLK synchronized to the S interface. Format 1, SCLK = 2.048 MHz, Format 2, SCLK = 256 kHz, Format 3, * SCLK = 512 kHz, Format 4, SCLK = 2.56 MHz. FIGURE ...

Page 9

Functional Description (Continued) * Note: DENR signal is available on pin 18 after using the PINDEF command (see Table 1 ). FIGURE 4. Digital System Interface Formats in TEM mode (DSI Master) Format 1 DS009143-14 Format 2 Format 3 Format ...

Page 10

Functional Description FIGURE 5. TP3240A Enhanced MICROWIRE Control Interface Timing Function Activation/Deactivation No Operation Power-Down (Note 6) Power-Up Deactivation Request Force INFO2 (NT only) Monitor Mode Activation Activation Request Device Modes NT Mode, Adaptive Sampling (Note 6) NT Mode, Fixed ...

Page 11

Functional Description (Continued) TABLE 4. Control Register Functions (Continued) Function D Channel Access D Channel Request, Class 1 Message D Channel Request, Class 2 Message D Channel Access Control Enable D-Channel Access Mechanism, TE Mode (Note 8) Disable D-Channel Access ...

Page 12

Functional Description (Continued) TABLE 4. Control Register Functions (Continued) Function Control Device State Reading Disable the Device State Output on the NOCST (Note 6) Control of Additional Interrupts Enable the Slip and RMFE Interrupts Disable the Slip and RMFE Interrupts ...

Page 13

Functional Description (Continued) a packet in the D channel, a received E bit does not match the last transmitted D bit, indicating a lost collision. AI This interrupt indicates that the interface has been successfully Activated in response to an ...

Page 14

Functional Description DIGITAL INTERFACE FORMATS DIF1) These instructions select the format of the Digital Interface timing, see Figure 3 and DIF2) DIF3) Figure 4 . DIF4) BCLK FREQUENCY SETTINGS BCLK1 These instructions change the frequency of a BCLK2 selected Digital ...

Page 15

Functional Description (Continued) MULTIFRAME TRANSMIT AND RECEIVE REGISTERS MFT1L) With the device in TE Mode, data entered in MFT1H) M1, M2, M3 and M4 bits of MTF1L is MFT2) transmitted towards the NT in multiframe bit MFR1) positions Q1, Q2, ...

Page 16

Functional Description 3. Contiguous B1+B2 (128 kbit/s) digital loopback (LBB1, LBB2) in TEM mode and in NT/TES modes if FSa is phase synchronous with FSb. 4. Contiguous B1+B2+D (144 kbit/s) digital loopback (LBD) in TEM mode and in NT/TES modes ...

Page 17

Functional Description (Continued being received, the loop is de-activated, Status Indica- tion type DI is set and the INT output pulled low to indicate De-activation. I.430 does not provide for Deactivation to be initiated by a TE. However, ...

Page 18

Functional Description EBIT0 command forces the E bit to 0 continuously to simu- late the effect of a busy D channel. The D channel access al- gorithm can be verified by releasing the E-bit control using the EBITNRM command. Alternatively, ...

Page 19

Functional Description (Continued multiframe counter (30 ms) in the TP3420A is enabled by the MFC6E command, and disabled with the MFC6D command. When the counter is enabled (MFC6E), an inter- rupt MFC is generated locally every 30 ms ...

Page 20

Functional Description TABLE 8. Codes for SC1, SC2 and Q Channel Messages with 3X Checking Enabled SCI Messages Received at TE S11 S12 S13 S14 Idle (NORMAL Loss-of-Power 1 1 Indication STP Self Test Pass 0 0 ...

Page 21

Functional Description (Continued) BIPOLAR VIOLATION DETECTION AND FECV MESSAGING VIA THE SC1 CHANNEL NT Mode A Receive Multiframe Error (RMFE) detector circuit in the TP3420A identifies any multiframes in which one or more bi- polar violations is received, indicating a ...

Page 22

Typical Applications www.national.com 22 ...

Page 23

Typical Applications (Continued) POPULAR MICROWIRE FORMATS The TP3420A enhanced MICROWIRE port supports two popular formats used in typical terminal equipment applica- tions. 1. CCLK idling LOW when the CS pin is inactive HIGH, pulsing LOW/HIGH/LOW for 8 clocks then returning ...

Page 24

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications GND CC Voltage Voltage at any Digital Input V Electrical Characteristics Unless otherwise noted: limits printed in bold characters are electrical testing limits at V ± ...

Page 25

Timing Characteristics Symbol Parameter MCLK SYSTEM CLOCK (See Figure Master Clock Frequency MCK Master Clock Tolerance MCLK/XTAL Input Clock Jitter t , Clock Pulse Width & Low for MCLK Rise and ...

Page 26

Timing Characteristics (Continued) Symbol Parameter DIGITAL SYSTEM INTERFACE (See Figure Hold Time, BCLK High HCFH to FS and FS High (Inputs Set up Time, FS and SFC a FSb Inputs to BCLK Low t ...

Page 27

Timing Diagrams (Continued) FIGURE 10. Timing Details for Digital System Interface FIGURE 11. Timing Details for TEM, DCKE Mode Definitions and Timing Conventions DEFINITIONS the d.c. input level above which input level is guaranteed ...

Page 28

Definitions and Timing Conventions (Continued the maximum d.c. output level which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region ...

Page 29

MFT1H FIFO, if not, then the data from the MFT1L register is sent. If both the buffers are full, then a third ...

Page 30

SC1 Messaging Sequence Time SC1 (ms) I430 Frame Content 0 (MFC INT) (LRS) 5 (LRS) 10 (LRS) 15 (LRS) 20 (LRS) 25 (LRS) 0 (MFC INT) (IDLE) 5 (IDLE) 10 (IDLE) 15 (IDLE) 20 (IDLE) 25 (IDLE) 0 (MFC INT) ...

Page 31

... Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number TP3420AJ NS Package Number J20A Molded Dual-In-Line Package (N) Order Number TP3420AN NS Package Number N20A 31 www.national.com ...

Page 32

... National Semiconductor Asia Pacific Customer Fax: +49 (0) 1 80-530 85 86 Response Group Email: europe.support@nsc.com Tel: 65-2544466 Fax: 65-2504466 Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Tel: +49 (0) 1 80-534 16 80 National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 ...

Related keywords