MC14536BCL Motorola, MC14536BCL Datasheet
MC14536BCL
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MC14536BCL Summary of contents
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... Plastic “P and D/DW” Packages: – 7.0 mW From 125 _ C Ceramic “L” Packages: – From 100 125 _ C CLOCK INH. 7 OSC. INHIBIT OUT 1 OUT 2 REV 3 1/94 MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 Value Unit – 0 18.0 V – 500 – ...
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... Adc 5.0 7.5 — — pF 0.010 5.0 — 150 Adc 0.020 10 — 300 0.030 20 — 600 Adc MOTOROLA CMOS LOGIC DATA ...
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... For proper operation and V out should be constrained to the range V SS Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA ( pF Symbol TLH , t THL 5 ...
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... TEST MODE The test mode configuration divides the 24 flip–flop stages into three 8–stage sections to facilitate a fast test sequence. The test mode is enabled when 8–Bypass, Set and Reset are at a high level. (See Figure 8.) MOTOROLA CMOS LOGIC DATA to ...
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... Set Don’t Care MOTOROLA CMOS LOGIC DATA TRUTH TABLES Stage Selected Stage Selected for Decode Out for Decode Out 8–Bypass FUNCTION TABLE Clock OSC Inh Inh Reset Out 1 Out — — Input Stage Selected Stage Selected for Decode Out for Decode Out ...
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... MC14536B 6 LOGIC DIAGRAM MOTOROLA CMOS LOGIC DATA ...
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... 100 1 0.1 1.0 10 100 EXTERNAL CAPACITANCE (pF) Figure 3. Typical C X versus Pulse Width @ 5.0 V 100 FORMULA FOR CALCULATING MICROSECONDS IS AS FOLLOWS 100 k 1.0 0.1 1.0 MOTOROLA CMOS LOGIC DATA 100 5 FUNCTION 2 1 120 k) 0.5 0.2 0.1 75 100 125 1.0 k 0.0001 Figure 2. RC Oscillator Frequency as a ...
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... In 1 Switches to a “1”. 0 Counter Ripples from an all “1” state to an all “0” state 50 90% 50% OUT 10% t PLH t PHL t TLH t THL SET RESET OUT 1 8–BYPASS INH MONO IN OUT 2 OSC INH DECODE OUT MOTOROLA CMOS LOGIC DATA ...
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... and D inputs, and the clock input period frequency division (where n = the number of stages selected from the truth table) is obtainable at Decode Out –divided output can be obtained at OUT 1 and OUT 2 . Figure 9. Time Interval Configuration Using an External Clock, Set, MOTOROLA CMOS LOGIC DATA + 8–BYPASS ...
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... Figure 10. Time Interval Configuration Using an External Clock, Reset, and Output Monostable to Achieve a Pulse Output MC14536B 8–BYPASS OUT RESET OUT 2 1 SET 7 CLOCK INH 15 MONO–IN 14 CLOCK INH 3 13 DECODE OUT (Divide–by–4 Configured .00247 0. sec MOTOROLA CMOS LOGIC DATA ...
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... After Reset goes low, the output remains low for the oscillator’s period. After the part times out, the output again goes high. Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and MOTOROLA CMOS LOGIC DATA +V 16 ...
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... C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7. 0.020 0.040 0.51 1.01 MOTOROLA CMOS LOGIC DATA ...
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...