EP610PC-15 Altera Corporation, EP610PC-15 Datasheet

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EP610PC-15

Manufacturer Part Number
EP610PC-15
Description
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer
Altera Corporation
Datasheet
Features
Altera Corporation
A-DS-CLASSIC-05
May 1999, ver. 5
Usable gates
Macrocells
Maximum user I/O pins
t
f
Table 1. Classic Device Features
PD
CNT
Complete device family with logic densities of 300 to 900 usable gates
(see
Device erasure and reprogramming with non-volatile EPROM
configuration elements
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
Programmable security bit for protection of proprietary designs
100% generically tested to provide 100% programming yield
Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
Software design support featuring the Altera
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
(ns)
(MHz)
Table
Feature
®
1)
EP610
EP610I
300
100
16
22
10
EP910
EP910I
76.9
450
24
38
12
®
MAX+PLUS
EPLD Family
Classic
Data Sheet
EP1810
®
900
48
64
20
50
II
745

Related parts for EP610PC-15

EP610PC-15 Summary of contents

Page 1

... May 1999, ver. 5 Features Altera Corporation A-DS-CLASSIC-05 ® Complete device family with logic densities of 300 to 900 usable gates (see Table 1) Device erasure and reprogramming with non-volatile EPROM configuration elements Fast pin-to-pin logic delays as low and counter frequencies as high as 100 MHz pins available in dual in-line package (DIP), plastic J-lead ...

Page 2

... EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow. Altera Corporation ...

Page 3

... Functional Description Altera Corporation For more information, see the Development System & Software Data The Classic architecture includes the following elements: Macrocells Programmable registers Output enable/clock select Feedback select Macrocells Classic macrocells, shown in both sequential and combinatorial logic operation. Eight product terms form a programmable-AND array that feeds an OR gate for combinatorial logic implementation ...

Page 4

... This mode allows registers to be individually clocked by any signal on the AND array. With both true and complement signals in the AND array, the register can be configured to trigger on a rising or falling edge. This product-term-controlled clock configuration also supports gated clock structures. Altera Corporation ...

Page 5

... Figure 3. Classic Feedback Multiplexer Configurations Global Feedback Multiplexer Q Global I/O EP610 EP610I EP910 EP910I Altera Corporation Figure 2. Classic Output Enable/Clock Select AND Array OE = Product Term CLK = Global AND Array OE = Enabled CLK = Product Term Feedback Select Each macrocell in a Classic device provides feedback selection that is controlled by the feedback multiplexer ...

Page 6

... Figure 4. Classic Timing Model Global Clock Input Delay Array Clock t IN Logic Array I/O Delay t IO Figure 4. Devices have fixed Delay t ICS Register Delay Delay t LAD t CLR Feedback Delay t FD Output Delay Altera Corporation ...

Page 7

... Altera Corporation Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal timing relationship for internal and external delay parameters. ...

Page 8

... Data from Logic Array Register Output to Logic Array Clock from Logic Array Data from Logic Array Output Pin 752 Input Mode PD1 PD2 LAD t CLR Global Clock Mode ICS Array Clock Mode ACH ASU AH Output Mode LAD LAD ACL High-Impedance Tri-State Altera Corporation ...

Page 9

... Option Generic Testing Device Programming Altera Corporation Many Classic devices contain a programmable Turbo Bit control the automatic power-down feature that enables the low-standby- power mode. When the Turbo Bit option is turned on, the low-standby- power mode is disabled. All AC values are tested with the Turbo Bit option turned on ...

Page 10

Notes: ...

Page 11

... INPUT 11 14 INPUT CLK2 GND 12 13 24-Pin SOIC EP610 Altera Corporation High-performance, 16-macrocell Classic EPLD – Combinatorial speeds with t – Counter frequencies 100 MHz – Pipelined data rates 125 MHz Programmable I/O architecture with inputs or 16 outputs and 2 clock pins EP610 and EP610I devices are pin-, function-, and programming ...

Page 12

... Each macrocell can access signals Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 ) versus frequency of EP610 CC Turbo Non-Turbo 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 80 MHz Frequency INPUT (27) 23 CLK2 (16) 13 (26) 22 (25) 21 (24) 20 (23) 19 (22) 18 (21) 17 (20) 16 (18) 15 INPUT (17) 14 Altera Corporation ...

Page 13

... Typical I CC Output 100 Current (mA 0.45 V Output Voltage (V) O EP610I EPLDs 100 80 60 Typical I CC Output Current (mA Output Voltage (V) O Altera Corporation Figure 10 shows the typical output drive characteristics of EP610 devices. EP610-25, EP610-30 & EP610-35 EPLDs I OL Typical 5 Output Current (mA 5.0 V ...

Page 14

... Note (6) Min 2.0 –0.3 (7) 2.4 (7) (8) , 3.84 (7) –10 –10 EP610I Unit Max 7 0 150 ° C 135 ° C 150 ° C 135 ° C EP610I Unit Max 5. 0 ° ° C 500 ns 500 ns Max Unit µA 10 µA Altera Corporation ...

Page 15

... Table 7. EP610I Device I CC Symbol Parameter I V supply current CC1 CC (non-Turbo, standby supply current CC2 CC (non-Turbo, active supply current CC3 CC (Turbo, active) Altera Corporation Note (9) Conditions 1.0 MHz 1.0 MHz OUT 1.0 MHz 1.0 MHz IN Notes (2), (10) Conditions ground, no load I ...

Page 16

... Measured with a device programmed as a 16-bit counter. 760 in this data book. + 0.5 V (EP610I) for input currents less than 100 mA and periods CC rise time is 50 ms. For EP610I devices, maximum V CC and ns and ns Table 3 on page 758 rise time is unlimited with CC parameter refers to low-level TTL OL Altera Corporation ...

Page 17

... I/O input pad and buffer delay IO t Logic array delay LAD t Output buffer and pad delay OD t Output buffer enable delay ZX t Output buffer disable delay XZ Altera Corporation Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20 devices. Conditions ( (5) (6) ...

Page 18

... Altera Corporation Unit 4.0 ns 7.0 ns 11.0 ns 4.0 ns 1.0 ns 11.0 ns Unit Adder (3) 30.0 ns 30.0 ns 30.0 ns 30 ...

Page 19

... MAX (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation Condition EP610-25 Min 11.0 10 ...

Page 20

... Unit Adder (3) 25.0 ns 25.0 ns 25.0 ns 25.0 ns 25.0 ns 0.0 MHz 25 ns 0.0 ns 0.0 ns 0.0 ns 0.0 ns 25.0 ns 0.0 MHz 25.0 ns 0.0 ns 0 25.0 ns 25.0 ns 0.0 MHz Altera Corporation ...

Page 21

... MAX (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation Conditions Table 3 on page 758. ...

Page 22

Notes: ...

Page 23

... Features Altera Corporation High-performance, 24-macrocell Classic EPLD – Combinatorial speeds with t – Counter frequencies 76.9 MHz – Pipelined data rates 125 MHz Programmable I/O architecture with inputs or 24 outputs EP910 and EP910I devices are pin-, function-, and programming file- compatible Programmable clock option for independent clocking of all registers ...

Page 24

... Macrocell 24 Figure 12). Each macrocell INPUT INPUT INPUT CLK2 (40) Macrocell 1 (38) Macrocell 2 (37) Macrocell 3 (36) Macrocell 4 (35) Macrocell 5 (34) Macrocell 6 Macrocell 7 (33) Macrocell 8 (32) Macrocell 9 (31) Macrocell 10 (30) Macrocell 11 (29) Macrocell 12 (28) INPUT INPUT INPUT Altera Corporation 39 (43) (42 (41) (24 (27) 24 (26) 23 (25) 22 ...

Page 25

... Drive characteristics may exceed shown curves. EP910 EPLDs Typical I O Output 30 Current (mA 0. Altera Corporation Figure 13 shows the typical supply current (I EP910 devices. Figure 13. I vs. Frequency of EP910 Devices CC 100 10 Typical I CC Active (mA) 1.0 0.1 Figure 14 shows the typical output drive characteristics of EP910 devices. EP910I EPLDs ...

Page 26

... Note (2) EP910 EP910I Max Min Max 4.75 5. 0.3 –0 0 100 (50) 500 100 (50) 500 Min Max 2 0.3 CC –0.3 0.8 2.4 3.84 0.45 –10 10 –10 10 Altera Corporation Unit ° C ° C ° C ° C Unit ° C ° Unit µA µA ...

Page 27

... When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic transitions occur for 75 ns after the last transition. (11) Measured with a device programmed as a 24-bit counter. Altera Corporation Note (6) Conditions ...

Page 28

... Altera Corporation Unit ( MHz MHz MHz ...

Page 29

... MAX (6) Measured with a device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation Condition Table 15 on page 770. ...

Page 30

... Altera Corporation Unit MHz MHz MHz ...

Page 31

... MAX (6) Measured with the device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation Condition Table 15 on page 770. ...

Page 32

Notes: ...

Page 33

... 68-Pin PGA EP1810 Altera Corporation High-performance, 48-macrocell Classic EPLD – Combinatorial speeds with t – Counter frequencies MHz – Pipelined data rates 62.5 MHz Programmable I/O architecture with inputs or 48 outputs Programmable clock option for independent clocking of all registers Macrocells individually programmable JK flipflops, or ...

Page 34

... EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant. Figure 16). EP1810 devices are divided of this data sheet for more Altera Corporation ...

Page 35

... Macrocell 18 29 (J10) Macrocell Macrocell 20 31 (H10) Macrocell Macrocell 22 33 (G10) Macrocell Macrocell 24 Altera Corporation Classic EPLD Family Data Sheet Macrocell 48 Macrocell 47 Macrocell 46 Macrocell 45 Macrocell 44 Macrocell 43 Macrocell 42 Macrocell 41 Macrocell 40 Macrocell 39 Macrocell 38 Macrocell 37 Global Bus Macrocell 36 Macrocell 35 Macrocell 34 Macrocell 33 ...

Page 36

... Frequency of EP1810 Devices CC EP1810 100 10 Typical I CC Active (mA) 1.0 0.1 Figure 18 shows the output drive characteristics of EP1810 devices. . EP1810-35 & EP1810-45 EPLDs I OL Typical 5 Output Current (mA Output Voltage (V) ) versus frequency for 5 kHz 100 kHz 1 MHz 10 MHz Frequency Output Voltage (V) O Altera Corporation 60 MHz 5 ...

Page 37

... Low-level output voltage OL I I/O pin leakage current of dedicated I input pins I Tri-state output leakage current OZ Altera Corporation Tables 23 through 27 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for EP1810 devices. Conditions With respect to ground With respect to ground ...

Page 38

... V. CC Table 24 on page 781. Min Max 160 Speed Min Typ Max Grade -20, -25 50 150 -35, -45 35 150 -20, -25 20 -35, - (40) -20, -25 180 225 (250) -35, -45 100 180 (240) parameter refers to low-level TTL OL Altera Corporation Unit Unit µA µ ...

Page 39

... Register setup time SU t Register hold time H t Array clock delay IC t Global clock delay ICS t Feedback delay FD t Register clear time CLR Altera Corporation Tables 28 through 31 show the timing parameters for EP1810-20, EP1810-25, EP1810-35, and EP1810-45 devices. Conditions (3) ( (4) (3) (3) ...

Page 40

... MHz Unit Adder (2) 6.0 0.0 ns 5.0 0.0 ns 28.0 30.0 ns 11.0 0.0 ns 11.0 0.0 ns 11.0 0.0 ns 10.0 0.0 ns 18.0 0.0 ns 28.0 30.0 ns 8.0 0.0 ns 7.0 –30.0 ns 32.0 30.0 ns Altera Corporation ...

Page 41

... The f values represent the highest frequency for pipelined data. MAX (6) Sample-tested only for an output change of 500 mV. Pin-Out Information Altera Corporation Table 24 on page 781. Table 32 provides pin-out information for EP1810 devices in 68-pin PGA packages. Table 32. EP1810 PGA Pin-Outs Pin Function ...

Page 42

Notes: ...

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