74LS373

Manufacturer Part Number74LS373
Description3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops 74LS373Octal D-type Transparent Latches(with three-state outputs) 74LS373OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 74LS373OCTAL TRANSPARENT LAT
ManufacturerNational Semiconductor
74LS373 datasheet
 


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General Description

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General Description

(Continued)
The eight latches of the DM54 74LS373 are transparent D-
type latches meaning that while the enable (G) is high the Q
outputs will follow the data (D) inputs When the enable is
taken low the output will be latched at the level of the data
that was set up
The eight flip-flops of the DM54 74LS374 are edge-trig-
gered D-type flip flops On the positive transition of the
clock the Q outputs will be set to the logic states that were
set up at the D inputs
Function Tables
DM54 74LS373
Output
Enable
D
Control
G
L
H
H
L
H
L
L
L
X
H
X
X
H
High Level (Steady State) L
e
Transition from low-to-high level Z
e
Q
The level of the output before steady-state input conditions were established
e
0
Logic Diagrams
DM54 74LS373
Transparent Latches
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
cantly
The output control does not affect the internal operation of
the latches or flip-flops That is the old data can be retained
or new data can be entered even while the outputs are off
DM54 74LS374
Output
Output
Clock
Control
H
L
L
L
Q
L
L
0
Z
H
X
Low Level (Steady State) X
Don’t Care
e
e
High Impedance State
e
DM54 74LS374
Positive-Edge-Triggered Flip-Flops
TL F 6431–3
2
D
Output
H
H
L
L
X
Q
0
X
Z
TL F 6431– 4