SDA5255 Siemens Semiconductor Group, SDA5255 Datasheet

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SDA5255

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SDA5255
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Manufacturer
Siemens Semiconductor Group
Datasheet

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ICs for Consumer Electronics
TVTEXT 8-Bit Microcontroller, ROMless-Version:
SDA 5250
TVTEXT 8-Bit Microcontroller, ROM-Versions:
SDA 5251
SDA 5252
SDA 5254
SDA 5255
Preliminary Data Sheet 1998-04-08

Related parts for SDA5255

SDA5255 Summary of contents

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ICs for Consumer Electronics TVTEXT 8-Bit Microcontroller, ROMless-Version: SDA 5250 TVTEXT 8-Bit Microcontroller, ROM-Versions: SDA 5251 SDA 5252 SDA 5254 SDA 5255 Preliminary Data Sheet 1998-04-08 ...

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SDA 525x Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) The layout of the document has been completely updated. Edition 1998-04-08 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße ...

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Table of Contents 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 6.3.4.2 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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General Description The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acquisition hardware modul, a display generator for “Level 1” TTX data and an 8 bit microcontroller running at 333 ns cycle time. The controller ...

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Programmable horizontal and vertical sync delay • Full screen background colour in outer screen • Double size / double width / double height characters Synchronization • Display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with ...

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Block Diagram Capture Compare Timer Watchdog Timer ADC PWM Memory C500 Management (MMU) CPU Figure 1 Block Diagram Semiconductor Group TTC VTX, VPS Acquisition Slicer TTD Extended Program Data Memory Unit RAM ROM 1 K Byte ...

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Pin Configurations 4.1 Pin Configuration P-MQFP-80-1 (ROMless-Version) 60 P0.5 61 P0.6 P0.7 P2.3 P2.2 P2.1 P2.0 V SSA FIL3 FIL1 70 FIL2 V DDA REF CVBS P3.7 P3.6 P3.5 P3.4 P3.3 P3 Figure 2 Pin Configuration P-MQFP-80-1 ...

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Pin Configuration P-SDIP-52-1 (ROM-Versions) Figure 3 Pin Configuration P-SDIP-52-1 (ROM-Versions) (top view) Semiconductor Group P3.1 1 P0.7 2 P0.6 3 P0.5 4 P0.4 5 P0.3 6 P0.2 7 P0 XTAL1 ...

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Pin Configuration P-MQFP-64-1 (ROM-Versions N.C. 49 P1.3 50 P1.2 51 P1 SSA FIL3 55 FIL1 56 FIL2 DDA I 59 REF CVBS 60 P2.3 61 P2.2 62 P2.1 63 ...

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Pin Configuration P-LCC-84-2 (Emulator-Version P0.6 54 P0.7 55 STOP_OCF 56 ENE 57 P2.3/ANA3 58 P2.2/ANA2 59 P2.1/ANA1 60 ...

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Pin Functions (ROM- and ROMless-Version) Table 1 Pin Functions (ROM- and ROMless-Version) Symbol Pin No. Pin No. P-SDIP- P-MQFP- 52-1 64 ...

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Table 1 Pin Functions (ROM- and ROMless-Version) (cont’d) Symbol Pin No. Pin No. P-SDIP- P-MQFP- 52-1 64 ...

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Table 1 Pin Functions (ROM- and ROMless-Version) (cont’d) Symbol Pin No. Pin No. P-SDIP- P-MQFP- 52-1 64-1 HS/ VS/P4 CVBS P4.1 – – REF DDA ...

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Table 2 Additional PINS for ROMless-Version Symbol Pin Nr. P-MQFP-80 A10 33 A11 30 A12 23 A13 24 A14 22 ...

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Functional Description 6.1 Acquisition 6.1.1 TTX/VPS Slicer The slicer extracts horizontal and vertical sync information and TTX data from the CVBS signal. The slicer includes an analog circuit for sync filtering and data slicing. Further there are two analog ...

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Acquisition Status Word TTX/VPS FCER FCOK LIN.(4...0) FCOK FCER TTX/VPS 6.1.3 Memory Interface The acquisition dual port interface manages the VBI memory write access request from the acquisition hardware and an asynchronous memory access request from the microcontroller. The acquisition ...

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Acquisition Control Registers The following sections gives an overview about special function registers ACQMS_1, ACQMS_2 and ACQSIR, with which slicer and acquisition can be controlled: Acquisition Mode and Status Register ACQMS_1 Acquisition Mode and Status Register Default after reset: ...

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Acquisition-Sync-Interrupt-Register ACQSIR Acquisition-Sync-Interrupt- Register Default after reset (MSB) EVENEN EVENST LIN24EN LIN24ST AVIREN AHIRST AHIREN AVIRST AVIREN LIN24ST LIN24EN EVENST EVENEN Comments Semiconductor Group ACQSIR 1 = acquisition horizontal sync interrupt request. This bit is set by the ...

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Display Generator The display features of SDA525x are similar to the Siemens SDA5248 TTX controller. The display generator reads character addresses and control characters from the display memory, selects the pixel information from the character ROM and translates it ...

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Table 3 Clear Page Bits row 25 /column ... row is interpreted as a blanked row ... row is received and displayed 24 0 6.2.6 Display Page Addressing ...

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Character Generator The character generator includes the character and control code decoder, the RAM interface and the RGB-, BLAN- and COR-signal generator. The display generator reads data from the display RAM and calculates appropriate data which drives the RGB ...

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Table 5 Serial Control Bytes B7, B6, B5, B4 B3, B2, B1 (1) Reset state at begin of each row. (2) Takes effect ...

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Display Special Function Registers The display generator includes 9 registers to select the different formats and functions. Display Horizontal Delay Register DHD Display Horizontal Delay Register Default after reset (MSB) HD.7 HD.6 HD.7 ... HD.0 Comments Display ...

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Display Transparent Control Register DTCR Display Transparent Control Register Default after reset (MSB) CORI CORO TRBO TRBI TRFO TRFI IBP ICRP CORO CORI Note: Outside of a box means outside of a box opened by control code sequence ...

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Display Mode Register DMOD Display Mode Register Default after reset: XXXX0000B (MSB) – – DSDW Bit Bit Note: This register is not readable. Thus, do not use read-modify-write operations like ANL, ORL to modify ...

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Display Mode Register 1 DMODE1 Display Mode Register 1 Default after reset (MSB) ST_TOP ST_DIS BD_0 BD_1_23 BD_24 DH.1 ... DH.0 CON ST_DIS ST_TOP Comments Semiconductor Group DMODE1 CON DH.1 DH Box characters in row 0 ...

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Display Mode Register 2 DMODE2 Display Mode Register 2 Default after reset (MSB) DTEST.2 DTEST.1 DTEST.0 C7 C10 DCHAP.2..0 DTEST.0 DTEST.1 DTEST.2 Comments Semiconductor Group DMODE2 DCHAP.2 DCHAP.1 DCHAP Header is handled as erased row (Suppress ...

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Language Control Register LANGC Language Control Register Default after reset (MSB) OSD_64 LANGC.6 LANGC.5 LANGC.4 LANGC.3 LANGC.2 LANGC.1 LANGC.0 LANGC.4... LANGC.0 LANGC.6... LANGC.5 OSD_64 Comments Semiconductor Group LANGC Language selection for text outside of an OSD window. 00000 ...

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Display Cursor Column Position Register DCCP Display Cursor Column Position Register Default after reset (MSB) – DC_EN DCCP.5 DC_EN DCCP.5...DCCP.0 Bit 7 Comments Display Cursor Row Position Register DCRP Display Cursor Row Position Register Default after reset: 00 ...

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Display Timing Control Register DTIM Display Timing Control Register Default after reset (MSB) BG_R BG_G BG_B LIN8 LIN9 SANDC EO_VS EO_P30 BG_R BG_G BG_B Semiconductor Group DTIM EO_P30 EO_VS line character mode (higher priority than ...

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Teletext-Sync-Interrupt-Register TTXSIR Teletext-Sync-Interrupt- Register Default after reset (MSB) – VSY DHIRST 1 = display horizontal sync interrupt request (set by positive DHIREN 1 = enable display horizontal sync interrupt requests. DVIRST 1 = display vertical sync interrupt request ...

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Sandcastle Decoder To fit the requirements of various applications the input circuit of the sandcastle decoder is programmable. Both slicing levels (V decoder function can be varied in a range of about 0.9 V and in addition there is ...

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NO 2/4 3/4 NO 2/5 3/5 2/6 3/6 2/7 3/7 2/8 3/8 2/9 3/9 2/A 3/F 2/B 3/B 2/C 3/C 3/D 2/E 3/E 2/F 3/F Figure 6 G0 Character Set Note: NO ...

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A/0 B/0 A/1 B/1 A/2 B/2 A/3 B/3 A/4 B/4 A/5 B/5 A/6 B/6 A/7 B/7 A/8 B/8 A/9 B/9 A/A B/A A/B B/B A/C B/C A/D B/D A/E B/E A/F B/F Figure 7 Character Set West Europe Semiconductor Group ...

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A/0 B/0 A/1 B/1 A/2 B/2 A/3 B/3 A/4 B/4 A/5 B/5 A/6 B/6 A/7 B/7 A/8 B/8 A/9 B/9 A/A B/A A/B B/B A/C B/C A/D B/D A/E B/E A/F B/F Figure 8 Character Set West Europe (Turkish) Semiconductor ...

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A/0 B/0 A/1 B/1 A/2 B/2 A/3 B/3 A/4 B/4 A/5 B/5 A/6 B/6 A/7 B/7 A/8 B/8 A/9 B/9 A/A B/A A/B B/B A/C B/C A/D B/D A/E B/E A/F B/F Figure 9 Character Set East Europe Semiconductor Group ...

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German English 2/3 2/3 2/4 2/4 4/0 4/0 5/B 5/B 5/C 5/C 5/D 5/D 5/E 5/E 5/F 5/F 6/0 6/0 7/B 7/B 7/C 7/C 7/D 7/D 7/E 7/E Figure 10 National Option Characters I Semiconductor Group Scandinavian Italian 2/3 2/3 ...

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Turkish 2/3 2/4 4/0 5/B 5/C 5/C 5/D 5/D 5/E 5/F 6/0 7/B 7/C 7/C 7/D 7/D 7/E Figure 11 National Option Characters II Semiconductor Group Polish Czechian 2/3 2/3 2/4 2/4 4/0 4/0 5/B 5/B 5/C 5/D 5/E 5/E ...

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Figure 12 OSD Characters Set (these characters are customized and thus left blank on this page) Note: Characters ... to ... can only be ...

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Figure 13 Graphics Character Set Semiconductor Group 3/0 6/0 7/0 3/1 6/1 7/1 3/2 6/2 7/2 3/3 6/3 7/3 3/4 6/4 7/4 3/5 6/5 7/5 ...

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Microcontroller 6.3.1 Architecture The CPU manipulates operands in two memory spaces: the program memory space, and the data memory space. The program memory address space is provided to accommodate relocatable code. The data memory address space is divided into ...

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CPU-Hardware Instruction Decoder Each program instruction is decoded by the instruction decoder. This unit generates the internal signals that control the functions of each unit within the CPU-section. These signals control the sources and destination of data, as well ...

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Boolean Processor The Boolean processor is an integral part of the processor architecture independent bit processor with its own instruction set, its own accumulator (the carry flag) and its own bit- addressable RAM and I/O. The bit ...

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Stack Pointer (SP) The 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. This is also the address of the next byte that will be popped. The SP is incremented during a push. ...

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Watchdog Timer For software- and hardware security, a watchdog timer is supplied, which resets the processor, if not cleared by software within a maximum time period. Pulse Width Modulation Unit Up to six lines of port 1 may be used ...

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OSC Figure 14 CPU-Timing Note: For CDC see Chapter “Advanced Function Register” on page 115. 6.3.1.3 Addressing Modes There are five general addressing modes operating on bytes. One of these five addressing modes, however, operates on both bytes and bits: ...

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Register Addressing Register addressing accesses the eight working registers (R0 – R7) of the selected register bank. The PSW-register flags RS1 and RS0 determine which register bank is enabled. The least significant three bits of the instruction opcode indicate which ...

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Memory Organization The processor memory is organized into two address spaces. The memory spaces are: – Program memory address space – 256 byte plus 128-byte internal data memory address space – Extended internal data memory (XRAM) for storing teletext ...

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Memory Extension (ROMless version only) The processor is prepared to extend its external program memory space up to 512 Kbytes (Figure 15 and 16). For easy handling of existing software and assemblers this space is split into 8 banks of ...

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Figure 16 Bank Organization MEX1 (94 ): Bank Control – CB18 MEX2 (95 ): Mode Control MB18 CB = Current Bank NB = Next Bank MM = Memory Mode MB = Memory Bank ...

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Table 9 Port 4 Configuration CB P4 Latch MOVC-Handling MOVC-instructions may operate in two different modes, that are selected by bit MM in MEX2 MOVC will access the ...

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In order to prevent loss of program control during deep subroutine nesting a warning bit “SF” (Stack Full) is set in MEX2 whenever a memory extension stack depth overflow is imminent. For example Figure 19 shows the data flows at ...

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More comfortable programming based on C-programs, require similar processing of the source programs or object files with respect to special considerations of the compiler. Figure 20 shows an assembler program run, performing the following actions: 1. Start at ...

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Internal Data RAM The internal data memory is divided into four blocks: the lower 128 byte of RAM, the upper 128 byte of RAM, the 128-byte Special Function Register (SFR) area and the Kbyte additional RAM ...

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Special Function Registers The special function register address space resides between addresses 128 and 255. All registers except the program counter and the four banks of eight working registers reside here. Memory mapping the special function registers allows them ...

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Internal DATA RAM 128 127 48 Addressable 47 127 Bits in RAM 7 32 (128 Bits BANK BANK R0 16 Registers R7 BANK BANK R0 0 SDA 5250, SDA 5254 and ...

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Table 11 Internal RAM-Bit Addresses RAM Byte (MSB) 256 ...

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Table 12 Special Function Register Bit Address Space Direct Byte Address – – – ...

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Table 13 Special Function Register Overview Special Function Register Description Arithmetic Registers Accumulator B-Register Program Status Word System Control Registers Stack Pointer Data Pointer (high byte) Data Pointer (low byte) Data Pointer Select Power Control I/O-Port Registers Port 0 Port ...

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Table 13 Special Function Register Overview (cont’d) Special Function Register Description Analog Digital Converter ADC-Control Register ADC-Data Register ADC-Start Register Pulse Width Modulator Registers Enable Register Counter Register (low byte) Counter Register (high byte) Compare Register 0 Compare Register 1 ...

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Table 13 Special Function Register Overview (cont’d) Special Function Register Description Display Control Registers Horizontal Delay Vertical Delay Transparent Control Mode 1 Register Mode 2 Register Sync Interrupt Request Reg. Language Control Cursor Column Position Cursor Row Position Display Timing ...

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Table 14 Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface Teletext Sync Signals Analog Digital Converter 6.3.4 Interrupt Control The information flags, which control the entire interrupt system, are stored in following ...

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Table 15 Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface Teletext Sync Signals Analog Digital Converter The timer 0 and timer 1 interrupts are generated by TF0 and TF1, which are set ...

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Display V Display H Start of EVEN FIELD Start of ACQ Line 24 (each field) ACQ V ACQ H Figure 22 Teletext Sync Signal Interrupt System Semiconductor Group TTXSIR.2 TTXSIR.3 Display V Interrupt DVIRST DVIREN TTXSIR.0 TTXSIR.1 Display H Interrupt ...

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Input Level and Interrupt Request Flag Registers: TCON.1 External INT 0 Interrupt RQST TCON.5 Internal Timer TCON.3 External INT 1 Interrupt RQST TCON.7 Internal Timer SCON 1/0 Internal ...

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Teletext Sync Interrupt Request Register TTXSIR Teletext Sync Interrupt Request Register Default after reset (MSB) – VSY VSY, HSY, PCLK DVIREN DVIRST DHIREN DHIRST Semiconductor Group TTXSIR HSY PCLK DVIREN These bits are no interrupt bits. They are ...

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Acquisition Sync Interrupt Request Register ACQSIR Acquisition Sync Interrupt Request Register Default after reset (MSB) EVENEN EVENST LIN24EN LIN24ST AVIREN EVENEN EVENST LIN24EN LIN24ST AVIREN AVIRST AHIREN AHIRST Semiconductor Group ACQSIR Enables or disables the even field interrupt ...

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Interrupt Enable Register IE Interrupt Enable Register Default after reset (MSB) EA EADC EA EADC ETSI ES ET1 EX1 ET0 EX0 Semiconductor Group IE ETSI ES ET1 Enables or disables all interrupts interrupt ...

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Interrupt Priority Register IP0 and IP1 Interrupt Priority Register Default after reset (MSB) – IP0.6 Interrupt Priority Register Default after reset (MSB) – IP1.6 Corresponding bit-locations in both registers are used to set the interrupt priority ...

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If two requests of different priority levels are received simultaneously, the request of higher priority level will be serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within ...

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External Interrupts The external interrupt request inputs (INT0 and INT1) can be programmed for either transition- activated or level-activated operation. Control of the external interrupts is provided by the four low- order bits of TCON as shown in the ...

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Interrupt Control Register Default after reset: XXXX0101 (MSB) – – EX1R EX1F EX0R EX0F – Transition-Activated Interrupts (IT0 = 1, IT1 = 1) The IE0, IE1 flags are set by a transition at INT0, INT1, respectively; they are cleared during ...

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Interrupt Task Function The processor records the active priority level(s) by setting internal flip-flop(s). Each interrupt level has its own flip-flop. The flip-flop corresponding to the interrupt level being serviced is reset when the processor executes a RETI-instruction. The ...

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Table 19 Instruction External interrupt generated immediately before (best) / after (worst) the pin is sampled (time until end of bus cycle). Current or next instruction finishes in 12-[6-] oscillator periods Next instruction is MUL or DIV Internal latency for ...

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V the Schmitt Trigger long enough to effect a complete reset. The time required is the oscillator start-up time plus 4 machine cycles. Attention: While reset is active and at least four machine cycles after rising ...

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Power Control Register PCON Power Control Register Default after reset: 000xxx00 (MSB) SMOD PDS PDS IDLS PDE IDLE SMOD Entering the idle mode is done by two consecutive instructions immediately following each other. The first instruction has to set bit ...

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The following instruction sequence may serve as an example: ORL PCON,#00000010 ORL PCON,#01000000 The instruction that sets bit PDS is the last instruction executed before going into power- down mode. If idle mode and power-down ...

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Chapter “DC- Characteristics” on page 129). In ports P1, P3 and P4 the output drivers provide source current for one oscillator period if, and only if, software updates the bit in ...

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Table 20 Read-Modify-Write Instructions Mnemonic Description ANL logical AND ORL logical OR XRL logical EX – OR JBC jump if bit = 1 and clear bit CPL complement bit INC increment DEC decrement DJNZ decrement and jump if not zero ...

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Timer/Counter 0: Mode Selection Timer/counter 0 can be configured in one of four operating modes, which are selected by bit-pairs (M1, M0) in TMOD-register (see page 83). – Mode 0 Putting timer/counter 0 into mode 0 makes it look like ...

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Timer/Counter 1: Mode Selection Timer/counter 1 can also be configured in one of four modes, which are selected by its own bitpairs (M1, M0) in TMOD-register. The serial port receives a pulse each time that timer/counter 1 overflows. This pulse ...

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Timer/Counter Mode Register Timer 0/1 Mode Register Default after reset (MSB) GATE C/T Timer 1 GATE C/T Table Operating Mode 0 0 SAB 8048 timer: “TLx” serves as five-bit prescaler 16-bit timer/counter: “THx” ...

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Timer/Counter Control Register Timer 0/1 Mode Register Default after reset (MSB) TF1 TR1 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Semiconductor Group TCON TF0 TR0 IE1 Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared ...

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OSC 12 T0 Pin 1 Gate INT0 Pin Figure 25 Timer/Counter 0 Mode 0: 13-Bit Counter . . OSC 12 T0 Pin 1 Gate INT0 Pin Figure 26 Timer/Counter 0 Mode 2: ...

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OSC fm T0 Pin 1 Gate INT0 Pin Figure 27 Timer/Counter 0 Mode 3: Two 8-Bit Counters Semiconductor Group CDC = 0 Machine Cycles fm CDC = 1 C ...

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Watchdog Timer To protect the systems against software upset, the user's program has to clear this watchdog within a previously programmed time period. If the software fails to do this periodical refresh of the watchdog timer, an internal hardware ...

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Watchdog Timer Control Bits Watchdog Timer Reload Register Default after reset (MSB) WDTREL.7 WDTREL.6 WDTREL.5 WDTREL.4 WDTREL.3 WDTREL.2 WDTREL.1 WDTREL.0 WDTREL.7 WDTREL.0 - WDTREL.6 Watchdog Timer Control Register Default after reset (MSB) WDTS SWDT WDTS SWDT ...

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Advanced Function Register AFR Advanced Function Register Default after reset: 00xxxxxx (MSB) CDC WDT CDC WDT AFR.0 - AFR.5 Semiconductor Group AFR See Chapter “Advanced Function Register” on page 115. Watchdog timer refresh flag. Set to ...

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Capture Compare Timer For easier infrared signal decoding, an additional Capture Compare Timer is implemented. A functional overview is given in following feature list: – 16-Bit-Counter with prescaler bits selectable via SFR – Counting rate: internal ...

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The registers RELH and RELL (SFR-address E2 CAPH and CAPL (SFR-addresses E4 registers. The reset value of these registers is undefined. 6.3.10 Serial Interface The serial port is full duplex, meaning it can transmit and receive simultaneously also ...

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Serial Port Control Register SCON Serial Port Control Register Default after reset (MSB) SM0 SM1 SM0 SM1 SM2 REN TB8 RB8 TI RI Semiconductor Group SCON SM2 REN TB8 Serial Port Mode Selection, see Table 22. Enables the ...

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Table 22 Serial Port Mode Selection SM0 SM1 Mode all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is ...

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Baud Rates The baud rate in mode 0 is fixed: f OSC Mode 0 baud rate = -------------- 6 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON (bit 7). ...

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More about Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/ received: 8 data bits (LSB first). Figure 28 shows a simplified functional diagram of the serial port in mode ...

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The transmission begins with activation of SEND, which puts ...

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Figures 32 and 34 show a functional diagram of the serial port in modes 2 and 3 and associated timings. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in ...

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Write to SBUF Clock & REN RI Figure 28 Serial Port Mode 0, Functional Diagram Semiconductor Group Internal Bus SBUF Zero Detector Start TX Control Send TX Clock TI Serial < Port Interrupt ...

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Transmit Figure 29 Serial Port Mode 0, Timing Semiconductor Group Receive 99 SDA 525x 1998-04-08 ...

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Write to SBUF Timer1 Overflow SMOD SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector RxD Figure 30 Serial Port Mode 1, Functional Diagram Semiconductor Group Internal Bus SBUF CL Zero Detector Start TX Control . ...

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Figure 31 Serial Port Mode 1, Timing Semiconductor Group Transmit 101 SDA 525x Receive 1998-04-08 ...

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Write to SBUF Phase 2 CLK SMOD SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector RxD Figure 32 Serial Port Mode 2, Functional Diagram Semiconductor Group Internal Bus TB8 Q S SBUF D CL Zero Detector Stop Bit Gen. ...

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Figure 33 Serial Port Mode 2, Timing Semiconductor Group Transmit 103 SDA 525x Receive 1998-04-08 ...

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Write to SBUF Timer1 Overflow SMOD SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector RxD Figure 34 Serial Port Mode 3, Functional Diagram Semiconductor Group Internal Bus TB8 SBUF CL Zero Detector Start TX Control . ...

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Figure 35 Serial Port Mode 3, Timing Semiconductor Group Transmit 105 SDA 525x Receive 1998-04-08 ...

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Pulse Width Modulation Unit (PWM) The on-chip-PWM unit consists of 6 quasi-8-Bit and 2 quasi-14-Bit PWM channels. Controlled via special function registers, each channel can be enabled individually. The base frequency of an 8-Bit channel is derived from the ...

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Table 24 Effect of PWEXTx-Bits for 14-Bit PWM PWEXTx Cycle Number ‘Stretched’ Bit 7 1,3,5,7,...,59,61,63 Bit 6 2,6,10,...,54,58,62 Bit 5 4,12,20,...,52,60 Bit 4 8,24,40,56 Bit 3 16,48 Bit 2 32 Bit 1 no effect Bit 0 no effect Table 25 ...

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PWM-Enable Register PWME PWM-Enable Register Default after reset (MSB PWM Compare Registers PWCOMP PWM Compare Registers Default after reset (MSB) Bit 7 Bit 6 ...

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PWM Compare Registers PWCOMP 6, 7 PWM Compare Registers Default after reset (MSB) Bit 7 Bit 6 Bit 7 - Bit 0 PWM Extension Registers PWEXT 6, 7 PWM Extension Registers Default after reset (MSB) Bit ...

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PWM Low Counter Registers PWCL PWM Low Counter Registers Default after reset (MSB) Bit 7 Bit 6 Bit 7 - Bit 0 PWM High Counter Registers PWCH PWM High Counter Registers Default after reset (MSB) Bit ...

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Internal Bus Figure 37 Block Diagram of Pulse Width Modulation Unit Semiconductor Group PWM-Timer E7 E6 Enable Register E1 PWM-Channel 0 8 Bit PWM-Channel 1 8 Bit PWM-Channel 2 8 Bit PWM-Channel 3 8 Bit PWM-Channel 4 8 Bit ...

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Analog Digital Converter The controller provides an A/D-converter with the following features: – 4 multiplexed input channels, which can also be used as digital inputs – 8-bit resolution – 8.89 to 28.4 s conversion time for 18 MHz oscillator ...

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OSC Figure 38 Internal System Clock of the ADC ADC-Start Register DAPR ADC-Start Register Default after reset (MSB) – – Only the address of DAPR is used to decode a start-of-conversion signal. No bits are implemented. ...

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ADC-Control Register ADCON ADC-Control Register Default after reset (MSB) PSC STADC This register is bit addressable. PSC STADC IADC BSY ADM ADCON.2 MX1, MX0 Table 26 ADC-Channel Select MX1 MX0 ...

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ADC-Data Register ADDAT ADC-Data Register Default after reset: undefined (MSB) AD7 AD6 AD (7-0) 6.3.13 Advanced Function Register Advanced Function Register Default after reset: 00xxxxxxB (MSB) CDC WDT CDC WDT AFR.0 – AFR.5 The machine cycle time is controlled by ...

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Instruction Set The assembly language uses the same instruction set and the same instruction opcodes as the 8051 microcomputer family. 6.3.14.1 Notes on Data Addressing Modes Rn – Working register R0 – R7. direct – 128 internal RAM-locations, any ...

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Instruction Set Description Table 27 Arithmetic Operations Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB ...

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Table 28 Logical Operations Mnemonic ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, ...

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Table 29 Data Transfer Operations Mnemonic MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV ...

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Table 30 Boolean Variable Manipulation Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Semiconductor Group Description Clear ...

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Table 31 Program and Machine Control Operations Mnemonic ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JMP @A + DPTR JZ rel JNZ rel JC rel JNC rel JB bit, rel JNB ...

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Instruction Opcodes in Hexadecimal Order Table 32 Instruction Opcodes in Hexadecimal Order Hex Code Number of Bytes ...

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Table 32 Instruction Opcodes in Hexadecimal Order (cont’d) Hex Code Number of Bytes ...

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Table 32 Instruction Opcodes in Hexadecimal Order (cont’d) Hex Code Number of Bytes ...

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Table 32 Instruction Opcodes in Hexadecimal Order (cont’d) Hex Code Number of Bytes ...

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Table 32 Instruction Opcodes in Hexadecimal Order (cont’d) Hex Code Number of Bytes ...

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Table 32 Instruction Opcodes in Hexadecimal Order (cont’d) Hex Code Number of Bytes ...

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Table 32 Instruction Opcodes in Hexadecimal Order (cont’d) Hex Code Number of Bytes ...

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Electrical Characteristics 7.1 Absolute Maximum Ratings Table 33 Parameter Voltage on any pin with respect to ground ( Power dissipation Ambient temperature under bias Storage temperature 7.2 DC-Characteristics Table 34 DC-Characteristics = ...

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Table 34 DC-Characteristics (cont’ Parameter Power down current (Sum and V -Pins) DD DDA Pin capacitance H-SC voltage L-SC voltage 1 L-SC voltage 2 Analog ...

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AC-Characteristics External Clock Drive XTAL1 / Quartz Clock Drive XTAL1 - XTAL2 Table Parameter Cycle time Address out to valid instr in Oscillator period External clock ...

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ALE Inst Figure 40 Program Memory Read Cycle Semiconductor Group ALAH t t ALIV PXAV t PXIX Inst IN t AVIV A0-16 132 SDA 525x Inst IN A0-16 UED04734 1998-04-08 ...

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OSD-Input/Output Timing Table 36 Parameter L-sandcastle time H-sandcastle time Horizontal offset Pixel width BLAN, COR Figure 41 OSD-Input/Output Timing Semiconductor Group Symbol 15 t SCL t 3 SCH SCH 83 t DOT t ...

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Display-Generator-Timing Table Parameter Hsync width End of visible screen area to Hsync ‘1’ Start of visible screen area to Hsync ‘0’ Delay between Hsync and R/G/B/BLAN/COR-lines 1) ...

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AC-Testing Input, Output, Float Waveforms AC testing inputs are driven at V Timing measurements are made at V timing purposes a port pin is no longer floating, when a 100 mV change from load voltage occurs 0.5 V ...

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Applications XTAL1 18 MHz 33 pF XTAL2 +5 V 8.2 k RST LCIN 6 LCOUT max. tolerance REF of LC-circuit 82 k Only ROMless Figure 44 Application Circuit for ...

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Package Outlines P-SDIP-52-1 Plastic Shrink Dual In-line Package 1.78 1.3 max 52 1 Index Marking Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group ...

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P-LCC-84-2 (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 138 SDA 525x Dimensions in mm 1998-04-08 ...

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P-MQFP-64-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 139 SDA 525x Dimensions in mm 1998-04-08 ...

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P-MQFP-80-1 (Plastic Metric Quad Flat Package) 0.65 0.3 ±0. Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our ...

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Index A ACC AC-Characteristics 131 ACQMS_1 61 ACQMS_2 61 ACQSIR 19, 61 Acquisition 5, 16 Acquisition Control Registers Acquisition hardware 16 Acquistion Mode and Status Register ADC-Control Register 114 ADC-Data Register 115 ADCON 61, 114 ADC-Start Register ...

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I I/O-Port Registers Immediate Addressing Infrared Timer Control Register Instruction Opcodes in Hexadecimal Order 122 Instruction Set 116 Instruction Set Description Internal Data Memory Address Space 57 Internal Data RAM 43, 55 Interrupt Control 63 Interrupt Control ...

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PWM Compare Registers PWM High Counter Registers PWME 61, 108 PWM-Enable Register R Read-Modify-Write 80 Register Addressing 48 Register-Indirect Addressing RELH 60 RELL 60 Response Time 74 S Sandcastle Control Register Sandcastle Decoder 33 SBUF 61 SCCON 33, 62 SCON ...

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