LC72722 Sanyo Semiconductor Corporation, LC72722 Datasheet
LC72722
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LC72722 Summary of contents
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... Ordering number : ENN6123A Overview The LC72722 and LC72722M, LC72722PM are single- chip system ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RDBS (Radio Broadcast Data System) standard. These ICs include band-pass filter, ...
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... Pin Assignment Block Diagram V REF +5V Vdda REFERENCE VOLTAGE Vssa MPXIN ANTIALIASING FILTER DO CL CCB MEMORY CONTROL T2 TEST LC72722, 72722M, 72722PM unit: mm 3045C-MFP24 0.15 (0.62) (0.75) SANYO: MFP24S V REF 1 24 SYR MPXIN Vdda Vssa FLOUT LC72722 CIN 6 ...
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... Synchronization and RAM address reset (active high) 14 Vddd Digital system power supply (+ Vssd Digital system ground Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications. LC72722, 72722M, 72722PM Function Serial data interface (CCB) I/O Pin circuit Vdda Output Vssa ...
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... Data latch change time Data output time Electrical Characteristics –40 to +85°C, Vssd = Vssa = 0 V Parameter Input resistance Internal feedback resistance Center frequency –3 dB bandwidth Gain LC72722, 72722M, 72722PM Symbol Conditions Vddd, Vdda: Vdda ≤ Vddd +0 max max CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC ...
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... Offset word detection flag (1 bit): OWD OWD Offset word detection 1 Detected 0 Not detected (protection function operating) LC72722, 72722M, 72722PM Symbol Conditions FLOUT : ∆f = ±7 kHz Att1 Att2 FLOUT : f < 45 kHz, f > 70 kHz Att3 FLOUT : f < 20 kHz Vref VREF : Vdda = CL, DI, CE, SYR, T1, T2 ...
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... When the error flags are 011 (indicating that correction is not possible) the data must be handled as invalid data. 8. RDS data (16 bits D15 This data is output with the MSB first and the LSB last. Caution: When error correction was not possible, the input data is output without change. LC72722, 72722M, 72722PM ...
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... Initial value: FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0 2. Synchronization detection method setting (1 bit Synchronization detection conditions 0 If, during 3 blocks, 2 blocks of offset words were detected in the correct order the offset words were detected in the correct order in 2 consecutive blocks. Initial value LC72722, 72722M, 72722PM IN1 data, first bit ...
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... Crystal oscillator frequency selection (1 bit 4.332 MHz 8.664 MHz Initial value LC72722, 72722M, 72722PM Normal write (See the description of the OWE bit.) After the reset is cleared, start writing from the data prior to the establishment of synchronization, i.e. the data in backward protection. RAM write conditions ...
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... Mode 1 (PT2 = 0) Pin T7 (TA detected High ( detected Low ( Traffic announcement code Mode 2 (PT2 = present Mode 3 (PT2 = 0) Pin T6 (ERROR) Correction not possible Errors corrected No errors LC72722, 72722M, 72722PM Decoding method T5 T6 RSFT ERROR 57K TP — — — — — — — — ...
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... CT0 RSFT control CT1 RDS-ID detection condition Initial values: CT0 = 0, CT1 = 0 RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing Timing 1 RDCL output RDDA output RSFT output 17 s LC72722, 72722M, 72722PM Pin T7 (BE0) Low (0) Low (0) Low (0) High (1) High (1) Low (0) High (1) High (1) The SYNC pin The RDS-ID pin ...
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... OUT (6C For the CL normal high state For the CL normal low state 2 LC72722, 72722M, 72722PM Data No No Data corrected errors errors corrected Tp1 Tp1 (MSB · Control data input mode, also referred to as “serial data input” mode · This is a 16-bit data input mode. ...
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... The CE, CL, DI, and DO pins can be connected to the corresponding pins on other ICs that use the CCB interface. (However, we recommend connecting the DO and CE pins separately if the number of available microcontroller ports allows it.) 3. Serial data I/O becomes possible after the crystal oscillator starts oscillation. LC72722, 72722M, 72722PM ≥ 0.75 µ < ...
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... Internal data latch CL: Normal low Internal data latch Parameter Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time CE high-level time Data latch transition time Data output time LC72722, 72722M, 72722PM Symbol Conditions t DI ...
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... One method is to read out data from the LC72722 and either check whether meaningful data has been read (if the LC72722 is not requesting a read, data consisting of all zeros will be read out) or check whether the DO level goes low within the 256 µs following the completion of the read (if the DO pin goes low, then the request was from another IC) ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 2002. Specifications and information herein are subject to change without notice. LC72722, 72722M, 72722PM REF SYR ...