CY7C63000A-PC Cypress Semiconductor Corporation., CY7C63000A-PC Datasheet
CY7C63000A-PC
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CY7C63000A-PC Summary of contents
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... CY7C63000A CY7C63001A CY7C63100A CY7C63101A Universal Serial Bus Microcontroller Cypress Semiconductor Corporation Document #: 38-08026 Rev. ** CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 3, 2002 ...
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... USB Physical Layer Characteristics ......................................................................................... 20 5.10.1 Low-Speed Driver Characteristics ................................................................................................... 20 5.10.2 Receiver Characteristics ................................................................................................................... 20 5.11 External USB Pull-Up Resistor .................................................................................................. 21 5.12 Instruction Set Summary ........................................................................................................... 21 6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 22 7.0 ELECTRICAL CHARACTERISTICS .............................................................................................. 23 8.0 SWITCHING CHARACTERISTICS ................................................................................................ 25 9.0 ORDERING INFORMATION .......................................................................................................... 27 10.0 PACKAGE DIAGRAMS ............................................................................................................... 28 Document #: 38-08026 Rev. ** CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A TABLE OF CONTENTS Page ...
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... Table 5-1. I/O Register Summary ......................................................................................................... 9 Table 5-2. Output Control Truth Table .............................................................................................. 13 Table 5-3. Interrupt Vector Assignments .......................................................................................... 15 Table 5-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0 .................... 18 Table 5-5. Instruction Set Map ........................................................................................................... 21 2 Document #: 38-08026 Rev. ** CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A LIST OF FIGURES LIST OF TABLES Page ...
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... USB optimized instruction set • Internal memory — 128 bytes of RAM — 2 Kbytes of EPROM (CY7C63000A, CY7C63100A) — 4 Kbytes of EPROM (CY7C63001A, CY7C63101A) • I/O ports — Integrated USB transceiver — Schmitt trigger I/O pins with internal pull-up — ...
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... RAM NOW™ 128-Byte USB PORT 0 Engine P0.0–P0.7 D+,D– PinConfigurations (Top View) P0 P0.5 P0 P1 D– XTALOUT CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A 8-bit Timer PORT 1 P1.0–P1.7 24-pin SOIC/QSOP P0 P0.5 P0.6 P0 P0.7 P0.3 4 P1.1 20 P1.0 5 P1.3 P1 P1.5 P1.4 ...
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... Port 1 bit 7 12 Ceramic resonator in 13 Ceramic resonator out 11 Connects to external R/C timing circuit for optional ‘suspend’ wakeup 16 USB data+ 15 USB data– 10 Programming voltage supply, tie to ground during normal operation 14 Voltage supply 9 Ground Description CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A range can vary CC Page ...
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... Program Memory Organization The program space of the CY7C63000A and CY7C63100A is 2 Kbytes each. For applications requiring more program space, the CY7C63001A and CY7C63101A each offer 4 Kbytes of EPROM. The program memory space is divided into two functional groups: interrupt vectors and program code. ...
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... DSP remapping after reset. Figure 5-2 illustrates the Data Memory Space. after reset DSP user firmware DSP Document #: 38-08026 Rev. ** Address 0x00 PSP 0x02 0x04 0x70 0x77 0x78 0x7F Figure 5-2. Data Memory Space CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A USB FIFO - Endpoint 0 USB FIFO - Endpoint 1 Page ...
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... The microcontroller resumes execution from ROM address 0x00 after a reset unless the Suspend bit (bit 3) of the Status and Control Register is set. Setting the Suspend bit stops the clock oscillator and the interrupt timers and powers down the microcon- Document #: 38-08026 Rev. ** CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A Read/Write ...
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... The suspend mode is terminated when one of the following three conditions occur: 1. USB activity 2. A GPIO interrupt 3. Cext interrupt Document #: 38-08026 Rev USBR POR SUSPEND R/W R/W R 8.192 ms Execution begins at Reset Vector 0x00 Figure 5-4. Watch Dog Reset (WDR) CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A Reserved Reserved RUN R Page ...
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... Document #: 38-08026 Rev Reserved Reserved Figure 5-5. The Cext Register (Address 0x22 T.5 T.4 T Figure 5-6. Timer Register (Address 0x23 Figure 5-7. Timer Block Diagram CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A b2 b1 Reserved Reserved T.2 T 1.024-ms interrupt 128- s interrupt Resonator Clock Timer Register b0 CEXT R/W ...
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... This resistor provides both the pull-up function and slew control. Two factors up currents during USB suspend mode, firmware must set ALL CC Isink DAC Disable Schmitt Trigger Figure 5-10. Block Diagram of an I/O Line CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A P0.2 P0.1 P0.0 R/W R/W ...
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... Pull-up Resistor (‘1’ PULL0.4 PULL0 PULL1.4 PULL1 UNUSED ISINK3 Figure 5-13. Port Isink Register for One GPIO Line CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A Interrupt Polarity High to Low Low to High High to Low Hi-Z Low to High b2 b1 PULL0.2 PULL0 PULL1.2 PULL1 ISINK2 ISINK1 Page PULL0.0 W ...
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... EP1IE EP0IE R/W R CLR D Q Enable [1] CLK CLR D Q Enable [6] CLK CLR D Q Enable [7] CLK CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A XTALOUT XTALIN 1024IE 128IE R/W R 128-ms CLR 128-ms IRQ 1-ms CLR 1-ms IRQ IRQ End P0 CLR End P0 IRQ End P1 CLR Interrupt End P1 IRQ Vector ...
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... IE0.5 IE0.4 IE0 IE1.5 IE1.4 IE1 CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A Function Reset 128- s timer interrupt 1.024-ms timer interrupt USB endpoint 0 interrupt USB endpoint 1 interrupt Reserved GPIO interrupt Wake-up interrupt b2 b1 IE0.2 IE0 IE1.2 IE1 Page IE0.0 W ...
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... Endpoint 0 is used to receive and transmit control (including setup) packets while Endpoint 1 is only used to transmit data packets. Document #: 38-08026 Rev. ** 1=L H Æ 0 Gate (1 input per GPIO pin CLR Global GPIO Interrupt Enable (Bit 6, Register 0x20) Figure 5-19. GPIO Interrupt Logic Block Diagram CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A GPIO Interrupt Flip-Flop CLR IRQ Interrupt Priority Interrupt Encoder Vector Page ...
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... Figure 5-21 COUNT3 COUNT2 COUNT1 R/W R/W Figure 5-21. USB Endpoint 0 RX Register (Address 0x14) Document #: 38-08026 Rev ADR5 ADR4 ADR3 R/W R/W R COUNT0 TOGGLE R/W R/W R CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A ADR2 ADR1 ADR0 R/W R/W R OUT SETUP R/W R/W R/W Page ...
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... Valid No OUT Error No OUT Valid No OUT Error No OUT Status No OUT N/Status No OUT Error ERR COUNT3 R/W R/W R/W CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A 0 0 USB Engine Response Toggle Count Interrupt Update Update Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...
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... ACK, and any other OUT with a STALL. The data is not written into the FIFO when this bit is set. This bit is cleared when a SETUP token is received by Endpoint 0. Document #: 38-08026 Rev EP1EN COUNT3 R/W R/W R ENOUTS STATOUTS R/W R CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A COUNT2 COUNT1 COUNT0 R/W R/W R FORCEJ FORCEK BUSACT R/W R ...
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... In addition to the differential receiver, there is a Document #: 38-08026 Rev. ** One Bit Time (1.5Mb/s) reflections and Figure 5-25. Low-speed Driver Signal Waveforms CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A Signal pins pass output spec levels with minimal ringing ...
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... XTALOUT 7.5kW 1% 0.1 F 6-MHz Resonator Pull-Up Resistor Port0 Port0 Switches, Devices, Etc. Port1 Port1 D– PP CEXT V CC XTALIN XTALOUT 6-MHz 0.1 F Resonator CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A 2.6 2.8 3.0 3.2 +4.35V (min) 4.7 F +3.3V 3.3V Reg 0.1 F ± 1.5 kW +4.35V (min.) 4.7 F Page ...
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... XOR [expr], XOR [X+expr], IOWX [X+expr CPL 1B 6 ASL 1C 4 ASR 1D 5 RLC 1E 13 RRC 1F 4 RET JNC Ax 5 JACC Bx 5 INDEX CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address 2A 5 ...
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... DC Voltage Applied to Outputs in High-Z state............................................................................................. –0. Max. Output Current into Port 1 Pins ................................................................................................................................... 60 mA Max. Output Current into Non-Port 1 Pins .......................................................................................................................... 10 mA Power Dissipation ..............................................................................................................................................................300 mW Static Discharge Voltage ................................................................................................................................................... >2000V [1] Latch-up Current .......................................................................................................................................................... >200 mA Document #: 38-08026 Rev. ** .................................................................................................................. –0.5V to +7.0V CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A CC CC Page +0.5V +0.5V ...
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... CC CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A = 4.0 to 5.25 volts CC Units Conditions mA A Resonator off, D– > Voh min Ceramic resonator ms ms Linear ramp on V pin [5,6] V 15k ± Gnd ...
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... V 6% 12% V 12% 30% V – 0.4 2.0 CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A = 4.0 to 5.25 volts CC Conditions [5] Vout = 2.0V DC, Port 0 only [5] Vout = 2.0V DC, Port 0 only [5] Vout = 2.0V DC, Port 1 only [5] Vout = 2.0V DC, Port 1 only [5] Vout = 0.4V DC, Port 1 only [5, 8] Vout = 2.0V DC, Port [9] Port 0 or Port 1 SB [10] Vout = 2 ...
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... Differential Transition t Source EOP Width eopt t Differential Driver Jitter udj1 t Differential Driver Jitter udj2 Notes: 14 200 (75 ns) to 600 pF (300 ns). load 15. Measured at crossover point of differential data signals. Document #: 38-08026 Rev. ** CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A Min. Max. Unit 166.67 166. CYC 0. CYC 75 300 ns ...
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... Figure 8-2. USB Data Signal Timing and Voltage Levels T PERIOD Differential Data Lines Document #: 38-08026 Rev CYC Figure 8-1. Clock Timing 90% 90% crs 10 Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 Figure 8-3. Receiver Jitter Tolerance CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A JR1 JR2 Page ...
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... T PERIOD Differential Data Lines Figure 8-4. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines 9.0 Ordering Information EPROM Ordering Code Size CY7C63000A-PC 2KB CY7C63000A-SC 2KB CY7C63001A-PC 4KB CY7C63001A-SC 4KB CY7C63100A-SC 2KB CY7C63101A-SC 4KB CY7C63101A-QC 4KB Document #: 38-08026 Rev. ** ...
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... Package Diagrams Document #: 38-08026 Rev. ** 20-Lead (300-Mil) Molded DIP P5 24-Lead Quarter Size Outline Q13 CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A 51-85011-A 51-85055-B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A ...
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... Document Title: CY7C63000A, CY7C63001A, CY7C63100A, CY7C63101A Universal Serial Bus Microcontroller Document Number: 38-08026 Issue REV. ECN NO. Date ** 116223 06/12/02 Document #: 38-08026 Rev. ** Orig. of Change DSG Change from Spec number: 38-00662 to 38-08026 CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A Description of Change Page ...