LC7218 Sanyo Semiconductor Corporation, LC7218 Datasheet

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LC7218

Manufacturer Part Number
LC7218
Description
PLL frequency synthesizer for electronic tuning in AV system
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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Ordering number : EN4758B
Overview
The LC7218, LC7218M and LC7218JM are PLL
frequency synthesizers for electronic tuning. The LC7218,
LC7218M and LC7218JM are optimal for AM/FM tuner
circuits that require high mounting densities.
Features
• These products feature a rich set of built-in functions for
Functions
• Programmable dividers
• Reference frequencies: Ten selectable frequencies:
• Output ports: 7 pins
• Input ports: 2 pins
• General-purpose counter: For measuring IF and other
• PLL unlock detection circuit
• Controller clock output: 400 kHz
• Clock time base output: 8 Hz
• Serial data I/O
• Package: LC7218: DIP24S
AV applications, including reference frequency and
unlock detection circuits, I/O ports and a general-
purpose counter.
— FMIN pin: 130 MHz at 70 mVrms and 160 MHz at
— AMIN pin: Pulse swallower and direct division
1, 5, 9, 10, 3.125, 6.25, 12.5 25, 50 and 100 kHz
Complementary outputs: 2 pins
N-channel open drain outputs: 5 pins
signals (Also used for station detection when
functioning as an IF counter.)
— HCTR pin: Frequency measurement (for inputs up
— LCTR pin: Frequency and period measurement
Detects phase differences of 0.55, 1.11, 2.22 and 3.33 µs.
— Supports CCB format communication with the
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
100 mVrms input (built-in prescaler)
techniques
to 70 MHz)
system controller.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
LC7218M: MFP24
LC7218JM: MFP24S
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
for Electronic Tuning in AV Systems
Package Dimensions
unit: mm
3067-DIP24S
LC7218, 7218M, 7218JM
PLL Frequency Synthesizer
63096HA (OT)/42895TH (OT) No. 4758-1/16
[LC7218]
SANYO: DIP24S
CMOS LSI

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LC7218 Summary of contents

Page 1

... Ordering number : EN4758B Overview The LC7218, LC7218M and LC7218JM are PLL frequency synthesizers for electronic tuning. The LC7218, LC7218M and LC7218JM are optimal for AM/FM tuner circuits that require high mounting densities. Features • These products feature a rich set of built-in functions for ...

Page 2

... Package Dimensions unit: mm 3045B-MFP24 [LC7218M] Pin Assignments LC7218, 7218M, 7218JM unit: mm 3112-MFP24S SANYO: MFP24 [LC7218JM] SANYO: MFP24S No. 4758-2/16 ...

Page 3

... Absolute Maximum Ratings 25°C, V Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature LC7218, 7218M, 7218JM Pin Symbols XIN, XOUT: FMIN, AMIN: CE, CL, DI, DO: Serial data I/O OUT0 to OUT6: Output ports IN0, IN1: HCTR, LCTR: PD1, PD2: ...

Page 4

... Frequency measurement 3. Frequency measurement 4. Period measurement 160 MHz/V ( 0.100 Vrms (minimum (4 MHz/V ( 0.100 Vrms (minimum) LC7218, 7218M, 7218JM = Conditions Crystal oscillator guaranteed operation DD CE, CL, DI, IN0, IN1 *4 LCTR: Pulse waveform, DC coupling CE, CL, DI, IN0, IN1 *4 LCTR DO, SYC OUT3 to OUT6, OUT0 ...

Page 5

... Three-state low level I OFFL off leakage current Input capacitance (1) DD Current drain I (2) DD Note: A capacitor of at least 2000 pF must be inserted between the power supply V LC7218, 7218M, 7218JM Conditions XIN FMIN AMIN HCTR LCTR LCTR CE, CL IN0, IN1 XIN: V ...

Page 6

... DO). • Input pin used when transferring serial data from the controller to the LC7218. • A total of 36 bits of data must be supplied to set up the LC7218 initial state. • Output pin used when transferring serial data to the controller from the LC7218. • A total of 28 bits from an internal shift register can be output in synchronization with the CL signal ...

Page 7

... The signal is supplied to a general-purpose 20-bit binary counter after passing through a divide-by-eight circuit. Therefore, the value of the counter is 1/8 of the frequency actually input to HCTR. • When HCTR is selected the LC7218 will function in frequency measurement mode and the measurement period can be selected to be either 60 or 120 ms. ( ms, 1: 120 ms) • ...

Page 8

... The LC7218 control data consists of 36 bits. All 36 bits must be input after power is applied to set up the LC7218 initial state. This is because the last two bits, while being unrelated to user functions, are data that switches the LSI test modes. Once the LC7218 has been initialized, the contents of the first 24 bits (D the contents of the last 12 bits (R0 to T1) by inputting data serial data input mode ...

Page 9

... DO Output Format (serial data output) The LC7218 includes a 28-bit internal shift register that can be used to output the following data from DO: the IN0 and IN1 input port states, the general-purpose counter (20-bit binary counter) and the unlock detection circuit state. The contents of the shift register is latched at the point that serial data output mode is selected. ...

Page 10

... Serial Data I/O Methods The LC7218 supports a total of three I/O modes: two control data input (serial data input) modes and one DO output (serial data output) mode. Data I/O is performed after the mode has been determined. The mode is selected by four data items (A set high ...

Page 11

... MHz. However, the times listed in the table that follows change since they are referenced to the crystal oscillator frequency. Note that care must be taken to prevent overtone oscillation when a 3.6 MHz crystal oscillator is used. LC7218, 7218M, 7218JM ≥ 1.5 µs, t ≥ 0 µs, t ≥ 1.5 µs, and t ...

Page 12

... LCTR pin. The general-purpose counter is started by setting CTEN the serial data. While the serial data is acquired internally in the LC7218 at the point the CE signal goes from high to low, the input to the HCTR or LCTR pin must be provided within 10 ms after CE goes low. ...

Page 13

... When mode 3 is specified and data is output through DO, DO will automatically go high after data output has completed, i.e., when CE goes low. • After that, DO goes low automatically when the IN0 signal changes state. (That is, DO can be used to check for changes in an external signal input to IN0.) LC7218, 7218M, 7218JM No. 4758-13/16 ...

Page 14

... Each bit is set to 1 according to øERROR as described above. UL2 : 3.33 µs UL3 : 0.55 µs øERROR: the phase difference (for a 7.2 MHz crystal) LC7218, 7218M, 7218JM and reset on the rising edge of CE rising edge can be read out in mode 3 (data output). and t is read out. ...

Page 15

... PLL fref = 50 kHz (FMIN selected) Programmable divider divisor Set N = 1007 (decimal). 3. AM, 10 kHz steps When the 1000 kHz (IF = +450 kHz) AM VCO = 1450 kHz PLL fref = 10 kHz (AMIN, low speed measurement selected) Programmable divider divisor Set N = 145 (decimal not care LC7218, 7218M, 7218JM No. 4758-15/16 ...

Page 16

... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of June, 1996. Specifications and information herein are subject to change without notice. LC7218, 7218M, 7218JM No. 4758-16/16 ...

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