LC7218

Manufacturer Part NumberLC7218
DescriptionPLL frequency synthesizer for electronic tuning in AV system
ManufacturerSanyo Semiconductor Corporation
LC7218 datasheet
 


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DO Output Format (serial data output)

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No.
Control block/data
• DV selects the local oscillator input pin. (FMIN or AMIN)
• SP switches the input frequency range when AMIN is selected.
Divider selection data
(5)
DV
DV
Sensitivity selection
1
(6)
data
0
SP
0
* don’t care
• SC selects the input pin (HCTR or LCTR) for the general-purpose counter.
• SF selects the measurement type (frequency or period) when LCTR is selected.
General-purpose
When HCTR is selected, SF is ignored and the LC7218 operates in frequency measurement
counter input pin
(7)
mode.
selection data
SC
DV
General-purpose
counter
1
(8)
frequency/period mode
0
switching data
0
SF
* don’t care
• GT selects the measurement time in frequency measurement mode and the number of periods
General-purpose
in period measurement mode.
counter count time
(9)
GT = 0: 60 ms/one period
selection data
GT = 1: 120 ms/two periods
GT
Time base output
• When TB is set to 1 an 8 Hz 40% duty clock time base signal is output from OUT0. O
(10)
control data
ignored in this mode.
TB
LSI test mode control
• T
and T
0
data
no user related functions. Both T
(11)
T
, T
Be sure to set both T
0
1

DO Output Format (serial data output)

The LC7218 includes a 28-bit internal shift register that can be used to output the following data from DO: the IN0 and
IN1 input port states, the general-purpose counter (20-bit binary counter) and the unlock detection circuit state.
The contents of the shift register is latched at the point that serial data output mode is selected.
No.
Data
Input port data
• The values of the IN0 and IN1 input ports are latched into I
(1)
I
and I
I
IN
0
1
0
General-purpose
• The C
19
(2)
counter binary data
C
20-bit binary counter MSB
19
C
to C
C
20-bit binary counter LSB
19
0
0
• The UL3 to UL0 data is latched from the unlock detection circuit.
UL0: 1.11
PLL unlock state data
(3)
UL1: 2.22
UL3 to UL0
UL2: 3.33
UL3: 0.55
LC7218, 7218M, 7218JM
Description
SP
Input pin
Input frequency range (MHz)
*
FMIN
10 to 130
1
AMIN
2 to 40
0
AMIN
0.5 to 10
SP
Input pin
Measurement type
HCTR
Frequency measurement (sine wave)
*
1
LCTR
Frequency measurement (sine wave)
0
LCTR
Period measurement (pulse waveform)
(frequency measurement/period measurement)
switch the LSI between test and normal operating modes. The test modes and have
1
and T
must always be set to 0.
0
1
and T
to 0 after power is applied.
0
1
Description
, I
IN
0
1
1
to C
data is latched from value of the general-purpose 20-bit binary counter.
0
These bits are set to 1 if a phase difference in excess of these times (in µs) was detected.
(for a 7.2 MHz crystal)
Related data
CTEN
CTEN
bit is
0
and I
.
0
1
No. 4758-9/16
GT
SC
SF
O
0